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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.all;
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library lpp;
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use lpp.amba_lcd_16x2_ctrlr.all;
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entity LCD_2x16_DRIVER is
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generic(
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OSC_Freq_MHz : integer:=60;
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Refresh_RateHz : integer:=5
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);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
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LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
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LCD_RS : out STD_LOGIC;
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LCD_RW : out STD_LOGIC;
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LCD_E : out STD_LOGIC;
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LCD_RET : out STD_LOGIC;
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LCD_CS1 : out STD_LOGIC;
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LCD_CS2 : out STD_LOGIC;
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STATEOUT: out std_logic_vector(3 downto 0);
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refreshPulse : out std_logic
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);
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end LCD_2x16_DRIVER;
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architecture Behavioral of LCD_2x16_DRIVER is
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type stateT is(Rst,Configure,IDLE,RefreshScreen);
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signal state : stateT;
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signal ShortTimePulse : std_logic;
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signal MidleTimePulse : std_logic;
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signal Refresh_RatePulse : std_logic;
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signal Start : STD_LOGIC;
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signal CFGM_LCD_RS : std_logic;
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signal CFGM_LCD_RW : std_logic;
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signal CFGM_LCD_E : std_logic;
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signal CFGM_LCD_DATA : std_logic_vector(7 downto 0);
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signal CFGM_Enable : std_logic;
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signal CFGM_completed : std_logic;
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signal FRMW_LCD_RS : std_logic;
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signal FRMW_LCD_RW : std_logic;
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signal FRMW_LCD_E : std_logic;
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signal FRMW_LCD_DATA : std_logic_vector(7 downto 0);
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signal FRMW_Enable : std_logic;
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signal FRMW_completed : std_logic;
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begin
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Counter : LCD_Counter
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generic map(OSC_Freq_MHz,Refresh_RateHz)
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port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
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ConfigModule : Config_Module
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port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
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FrameWriter : FRAME_WRITER
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port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
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STATEOUT(0) <= '1' when state = Rst else '0';
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STATEOUT(1) <= '1' when state = Configure else '0';
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STATEOUT(2) <= '1' when state = IDLE else '0';
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STATEOUT(3) <= '1' when state = RefreshScreen else '0';
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refreshPulse <= Refresh_RatePulse;
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Start <= '1';
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process(reset,clk)
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begin
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if reset = '0' then
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LCD_data <= (others=>'0');
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LCD_RS <= '0';
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LCD_RW <= '0';
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LCD_RET <= '0';
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LCD_CS1 <= '0';
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LCD_CS2 <= '0';
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LCD_E <= '0';
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state <= Rst;
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CFGM_Enable <= '0';
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FRMW_Enable <= '0';
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elsif clk'event and clk ='1' then
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case state is
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when Rst =>
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LCD_data <= (others=>'0');
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LCD_RS <= '0';
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LCD_RW <= '0';
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LCD_E <= '0';
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CFGM_Enable <= '1';
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FRMW_Enable <= '0';
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if Refresh_RatePulse = '1' then
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state <= Configure;
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end if;
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when Configure =>
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LCD_data <= CFGM_LCD_data;
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LCD_RS <= CFGM_LCD_RS;
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LCD_RW <= CFGM_LCD_RW;
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LCD_E <= CFGM_LCD_E;
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CFGM_Enable <= '0';
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if CFGM_completed = '1' then
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state <= IDLE;
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end if;
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when IDLE =>
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if Refresh_RatePulse = '1' then
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state <= RefreshScreen;
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FRMW_Enable <= '1';
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end if;
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LCD_RS <= '0';
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LCD_RW <= '0';
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LCD_E <= '0';
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LCD_data <= (others=>'0');
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when RefreshScreen =>
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LCD_data <= FRMW_LCD_data;
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LCD_RS <= FRMW_LCD_RS;
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LCD_RW <= FRMW_LCD_RW;
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LCD_E <= FRMW_LCD_E;
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FRMW_Enable <= '0';
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if FRMW_completed = '1' then
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state <= IDLE;
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end if;
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end case;
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end if;
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end process;
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end Behavioral;
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