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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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---TDODO => Clean Enable pulse FSM
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.all;
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library lpp;
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use lpp.amba_lcd_16x2_ctrlr.all;
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use lpp.lcd_16x2_cfg.all;
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entity LCD_16x2_DRIVER is
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generic(
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OSC_Freq_KHz : integer:=50000
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);
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Port(
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reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
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SYNCH : out LCD_DRVR_SYNCH_BUSS;
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DRIVER_CMD : in LCD_DRVR_CMD_BUSS
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);
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end LCD_16x2_DRIVER;
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architecture Behavioral of LCD_16x2_DRIVER is
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type stateT is (idle,Enable0,Enable1,Enable2,tempo);
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signal state : stateT;
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constant trigger_4us : integer := 5;
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constant trigger_100us : integer := 100;
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constant trigger_4ms : integer := 4200;
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constant trigger_20ms : integer := 20000;
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signal i : integer :=0;
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signal reset_i : std_logic := '0';
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signal tempoTRIG : integer :=0;
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signal clk_1us : std_logic;
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signal clk_1us_reg : std_logic;
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begin
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CLK0: LCD_CLK_GENERATOR
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generic map(OSC_Freq_KHz)
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Port map( clk,reset,clk_1us);
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process(clk_1us,reset_i)
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begin
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if reset_i = '0' then
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i <= 0;
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elsif clk_1us'event and clk_1us ='1' then
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i <= i+1;
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end if;
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end process;
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LCD_CTRL.LCD_RW <= '0';
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process(clk,reset)
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begin
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if reset = '0' then
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state <= idle;
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LCD_CTRL.LCD_E <= '0';
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SYNCH.DRVR_READY <= '0';
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SYNCH.LCD_INITIALISED <= '0';
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reset_i <= '0';
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elsif clk'event and clk = '1' then
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case state is
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when idle =>
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SYNCH.LCD_INITIALISED <= '1';
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LCD_CTRL.LCD_E <= '0';
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if DRIVER_CMD.Exec = '1' then
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state <= Enable0;
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reset_i <= '1';
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SYNCH.DRVR_READY <= '0';
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LCD_CTRL.LCD_DATA <= DRIVER_CMD.Word;
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LCD_CTRL.LCD_RS <= DRIVER_CMD.CMD_Data;
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case DRIVER_CMD.Duration is
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when Duration_4us =>
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tempoTRIG <= trigger_4us;
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when Duration_100us =>
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tempoTRIG <= trigger_100us;
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when Duration_4ms =>
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tempoTRIG <= trigger_4ms;
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when Duration_20ms =>
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tempoTRIG <= trigger_20ms;
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when others =>
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tempoTRIG <= trigger_20ms;
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end case;
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else
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SYNCH.DRVR_READY <= '1';
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reset_i <= '0';
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end if;
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when Enable0 =>
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if i = 1 then
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reset_i <= '0';
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LCD_CTRL.LCD_E <= '1';
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state <= Enable1;
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else
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reset_i <= '1';
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LCD_CTRL.LCD_E <= '0';
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end if;
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when Enable1 =>
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if i = 2 then
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reset_i <= '0';
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LCD_CTRL.LCD_E <= '0';
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state <= Enable2;
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else
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reset_i <= '1';
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LCD_CTRL.LCD_E <= '1';
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end if;
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when Enable2 =>
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if i = 1 then
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reset_i <= '0';
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LCD_CTRL.LCD_E <= '0';
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state <= tempo;
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else
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reset_i <= '1';
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LCD_CTRL.LCD_E <= '0';
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end if;
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when tempo =>
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if i = tempoTRIG then
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reset_i <= '0';
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state <= idle;
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else
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reset_i <= '1';
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end if;
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end case;
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end if;
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end process;
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end Behavioral;
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