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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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library lpp;
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use lpp.amba_lcd_16x2_ctrlr.all;
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package LCD_16x2_CFG is
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constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
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constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
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constant RetHome : std_logic_vector(7 downto 0):= X"02";
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constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
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constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0E";
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constant CursorON : std_logic_vector(7 downto 0):= X"0E";
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constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
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--===========================================================|
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--======L C D D R I V E R T I M I N G C O D E=====|
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--===========================================================|
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constant Duration_4us : std_logic_vector(1 downto 0) := "00";
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constant Duration_100us : std_logic_vector(1 downto 0) := "01";
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constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
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constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
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end LCD_16x2_CFG;
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