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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09:21:03 10/19/2010
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-- Design Name:
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-- Module Name: FRAME_CLK_GEN - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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library lpp;
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use lpp.amba_lcd_16x2_ctrlr.all;
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entity FRAME_CLK_GEN is
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generic(OSC_freqKHz : integer := 50000);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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FRAME_CLK : out STD_LOGIC);
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end FRAME_CLK_GEN;
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architecture Behavioral of FRAME_CLK_GEN is
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Constant Goal_FRAME_CLK_FREQ : integer := 20;
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Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
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signal CPT : integer := 0;
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signal FRAME_CLK_reg : std_logic :='0';
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begin
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FRAME_CLK <= FRAME_CLK_reg;
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process(reset,clk)
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begin
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if reset = '0' then
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CPT <= 0;
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FRAME_CLK_reg <= '0';
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elsif clk'event and clk = '1' then
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if CPT = FRAME_CLK_TRIG then
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CPT <= 0;
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FRAME_CLK_reg <= not FRAME_CLK_reg;
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else
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CPT <= CPT + 1;
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end if;
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end if;
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end process;
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end Behavioral;
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