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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.cic_pkg.ALL;
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USE lpp.data_type_pkg.ALL;
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ENTITY cic_lfr IS
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GENERIC(
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tech : INTEGER := 0;
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use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
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data_out_16_valid : OUT STD_LOGIC;
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data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
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data_out_256_valid : OUT STD_LOGIC
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);
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END cic_lfr;
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ARCHITECTURE beh OF cic_lfr IS
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SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL sample_temp : sample_vector(3 DOWNTO 0,15 DOWNTO 0);
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SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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-- SEL_SAMPLE
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-----------------------------------------------------------------------------
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all_bit: FOR I IN 15 DOWNTO 0 GENERATE
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sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
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sample_temp(1,I) <= data_in(3,I) WHEN sel_sample(0) = '0' ELSE data_in(4,I);
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sample_temp(2,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE data_in(2,I);
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sample_temp(3,I) <= sample_temp(1,I) WHEN sel_sample(1) = '0' ELSE data_in(5,I);
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sample(I) <= sample_temp(2,I) WHEN sel_sample(2) = '0' ELSE sample_temp(3,I);
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END GENERATE all_bit;
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END beh;
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