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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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library esa;
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use esa.memoryctrl.all;
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use work.config.all;
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library lpp;
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use lpp.lpp_amba.all;
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use lpp.lpp_memory.all;
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use lpp.lpp_uart.all;
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use lpp.lpp_matrix.all;
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use lpp.lpp_delay.all;
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use lpp.lpp_fft.all;
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use lpp.fft_components.all;
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use lpp.lpp_ad_conv.all;
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use lpp.iir_filter.all;
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use lpp.general_purpose.all;
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use lpp.Filtercfg.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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clk50MHz : in std_ulogic;
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reset : in std_ulogic;
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ramclk : out std_logic;
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ahbrxd : in std_ulogic; -- DSU rx data
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ahbtxd : out std_ulogic; -- DSU tx data
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dsubre : in std_ulogic;
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dsuact : out std_ulogic;
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urxd1 : in std_ulogic; -- UART1 rx data
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utxd1 : out std_ulogic; -- UART1 tx data
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errorn : out std_ulogic;
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address : out std_logic_vector(18 downto 0);
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data : inout std_logic_vector(31 downto 0);
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gpio : inout std_logic_vector(6 downto 0); -- I/O port
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nBWa : out std_logic;
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nBWb : out std_logic;
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nBWc : out std_logic;
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nBWd : out std_logic;
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nBWE : out std_logic;
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nADSC : out std_logic;
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nADSP : out std_logic;
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nADV : out std_logic;
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nGW : out std_logic;
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nCE1 : out std_logic;
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CE2 : out std_logic;
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nCE3 : out std_logic;
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nOE : out std_logic;
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MODE : out std_logic;
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SSRAM_CLK : out std_logic;
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ZZ : out std_logic;
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---------------------------------------------------------------------
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--- AJOUT TEST ------------------------In/Out-----------------------
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---------------------------------------------------------------------
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-- UART
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UART_RXD : in std_logic;
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UART_TXD : out std_logic;
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-- ADC
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ADC_in : in AD7688_in(4 downto 0);
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ADC_out : out AD7688_out;
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Bias_Fails : out std_logic;
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-- CNA
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-- DAC_SYNC : out std_logic;
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-- DAC_SCLK : out std_logic;
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-- DAC_DATA : out std_logic;
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-- Diver
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SPW1_EN : out std_logic;
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SPW2_EN : out std_logic;
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TEST : out std_logic_vector(3 downto 0);
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---------------------------------------------------------------------
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led : out std_logic_vector(1 downto 0)
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);
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end;
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architecture Behavioral of leon3mp is
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constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
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CFG_GRETH+CFG_AHB_JTAG;
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constant maxahbm : integer := maxahbmsp;
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--Clk & Rst g�n�
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signal vcc : std_logic_vector(4 downto 0);
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signal gnd : std_logic_vector(4 downto 0);
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signal resetnl : std_ulogic;
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signal clk2x : std_ulogic;
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signal lclk : std_ulogic;
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signal lclk2x : std_ulogic;
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signal clkm : std_ulogic;
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signal rstn : std_ulogic;
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signal rstraw : std_ulogic;
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signal pciclk : std_ulogic;
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signal sdclkl : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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--- AHB / APB
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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--UART
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signal ahbuarti : uart_in_type;
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signal ahbuarto : uart_out_type;
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signal apbuarti : uart_in_type;
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signal apbuarto : uart_out_type;
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--MEM CTRLR
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdo : sdram_out_type;
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--IRQ
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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--Timer
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signal gpti : gptimer_in_type;
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signal gpto : gptimer_out_type;
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--GPIO
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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--DSU
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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---------------------------------------------------------------------
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--- AJOUT TEST ------------------------Signaux----------------------
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---------------------------------------------------------------------
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-- FIFOs
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signal FifoIN_Full : std_logic_vector(4 downto 0);
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signal FifoIN_Empty : std_logic_vector(4 downto 0);
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signal FifoIN_Data : std_logic_vector(79 downto 0);
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signal FifoINT_Full : std_logic_vector(4 downto 0);
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signal FifoINT_Data : std_logic_vector(79 downto 0);
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signal FifoOUT_FullV : std_logic;
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signal FifoOUT_Full : std_logic_vector(0 downto 0);
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-- MATRICE SPECTRALE
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signal Matrix_Write : std_logic;
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signal Matrix_WriteV : std_logic_vector(0 downto 0);
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signal Matrix_Read : std_logic_vector(1 downto 0);
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signal Matrix_Result : std_logic_vector(31 downto 0);
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signal TopSM_Start : std_logic;
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signal TopSM_Statu : std_logic_vector(3 downto 0);
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signal TopSM_Read : std_logic_vector(4 downto 0);
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signal TopSM_Data1 : std_logic_vector(15 downto 0);
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signal TopSM_Data2 : std_logic_vector(15 downto 0);
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-- FFT
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signal Drive_Write : std_logic;
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signal Drive_Read : std_logic_vector(4 downto 0);
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signal Drive_DataRE : std_logic_vector(15 downto 0);
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signal Drive_DataIM : std_logic_vector(15 downto 0);
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signal Start : std_logic;
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signal FFT_Load : std_logic;
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signal FFT_Ready : std_logic;
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signal FFT_Valid : std_logic;
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signal FFT_DataRE : std_logic_vector(15 downto 0);
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signal FFT_DataIM : std_logic_vector(15 downto 0);
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signal Link_Read : std_logic;
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signal Link_Write : std_logic_vector(4 downto 0);
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signal Link_ReUse : std_logic_vector(4 downto 0);
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signal Link_Data : std_logic_vector(79 downto 0);
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-- ADC
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signal SmplClk : std_logic;
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signal ADC_DataReady : std_logic;
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signal ADC_SmplOut : Samples_out(4 downto 0);
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signal enableADC : std_logic;
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signal WG_Write : std_logic_vector(4 downto 0);
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signal WG_ReUse : std_logic_vector(4 downto 0);
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signal WG_DATA : std_logic_vector(79 downto 0);
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signal s_out : std_logic_vector(79 downto 0);
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signal fuller : std_logic_vector(4 downto 0);
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signal reader : std_logic_vector(4 downto 0);
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signal try : std_logic_vector(1 downto 0);
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signal TXDint : std_logic;
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-- IIR Filter
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signal sample_clk_out : std_logic;
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---------------------------------------------------------------------
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constant IOAEN : integer := CFG_CAN;
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constant boardfreq : integer := 50000;
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begin
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---------------------------------------------------------------------
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--- AJOUT TEST -------------------------------------IPs-------------
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---------------------------------------------------------------------
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led(1 downto 0) <= gpio(1 downto 0);
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--- COM USB ---------------------------------------------------------
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-- MemIn0 : APB_FifoWrite
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-- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
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-- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
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--
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-- BUF0 : APB_USB
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-- generic map (6,6,DataMax => 1024)
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-- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
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--
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-- MemOut0 : APB_FifoRead
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-- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
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-- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
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--
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--slrd <= usb_Read;
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--slwr <= usb_Write;
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--- CNA -------------------------------------------------------------
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-- CONV : APB_CNA
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-- generic map (5,5)
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-- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
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--TEST(0) <= SmplClk;
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--TEST(1) <= WG_Write(0);
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--TEST(2) <= Fuller(0);
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--TEST(3) <= s_out(s_out'length-1);
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SPW1_EN <= '1';
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SPW2_EN <= '0';
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--- CAN -------------------------------------------------------------
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Divider : Clk_divider
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generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
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Port map(clkm,rstn,SmplClk);
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ADC : AD7688_drvr
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generic map (ChanelCount => 5, clkkHz => 24_576)
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port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
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WG : WriteGen_ADC
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port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
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enableADC <= gpio(0);
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Bias_Fails <= '0';
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WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
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-- MemIn :lppFIFOx5
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-- generic map(Data_sz => 16, Enable_ReUse => '0')
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-- port map(rstn,clkm,clkm,WG_ReUse,WG_Write,reader,WG_DATA,FifoIN_Data,FifoIN_Full,FifoIN_Empty);
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MemIn : APB_FIFO
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generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
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port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
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--- FFT -------------------------------------------------------------
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-- MemIn : APB_FIFO
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-- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
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-- port map (clkm,rstn,clkm,clkm,Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(6));
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Start <= not rstn;
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DRIVE : Driver_FFT
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generic map(Data_sz => 16)
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port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Full,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM);
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FFT : CoreFFT
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generic map(
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LOGPTS => gLOGPTS,
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LOGLOGPTS => gLOGLOGPTS,
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WSIZE => gWSIZE,
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TWIDTH => gTWIDTH,
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DWIDTH => gDWIDTH,
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TDWIDTH => gTDWIDTH,
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RND_MODE => gRND_MODE,
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SCALE_MODE => gSCALE_MODE,
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PTS => gPTS,
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HALFPTS => gHALFPTS,
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inBuf_RWDLY => gInBuf_RWDLY)
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port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
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LINK : Linker_FFT
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generic map(Data_sz => 16)
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port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);
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--- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
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MemInt : lppFIFOx5
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generic map(Data_sz => 16, Enable_ReUse => '1')
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port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
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Matrix_WriteV(0) <= not Matrix_Write;
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FifoOUT_FullV <= FifoOUT_Full(0);
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TopSM : TopMatrix_PDR
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generic map (Input_SZ => 16)
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port map (clkm,rstn,FifoINT_Data,FifoINT_Full,Matrix_Read,Matrix_Write,TopSM_Data1,TopSM_Data2,TopSM_Start,TopSM_Read,TopSM_Statu);
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SM : SpectralMatrix
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generic map (Input_SZ => 16, Result_SZ => 32)
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port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,FifoOUT_FullV,Matrix_Read,Matrix_Write,Matrix_Result);
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--- FIFO -------------------------------------------------------------
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MemOut : APB_FIFO
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generic map (pindex => 15, paddr => 15, FifoCnt => 1, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
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port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Matrix_WriteV,open,FifoOUT_Full,open,Matrix_Result,open,open,apbi,apbo(15));
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Memtest : APB_FIFO
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generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 1)
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port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(9));
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--- UART -------------------------------------------------------------
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COM0 : APB_UART
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generic map (pindex => 5, paddr => 5)
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port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD);
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--- DELAY ------------------------------------------------------------
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Delay0 : APB_Delay
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generic map (pindex => 4, paddr => 4)
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port map (clkm,rstn,apbi,apbo(4));
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--- IIR Filter -------------------------------------------------------
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Test(0) <= sample_clk_out;
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IIR1: APB_IIR_Filter
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generic map(
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tech => CFG_MEMTECH,
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pindex => 8,
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paddr => 8,
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Sample_SZ => Sample_SZ,
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ChanelsCount => ChanelsCount,
|
|
|
Coef_SZ => Coef_SZ,
|
|
|
CoefCntPerCel => CoefCntPerCel,
|
|
|
Cels_count => Cels_count,
|
|
|
virgPos => virgPos
|
|
|
)
|
|
|
port map(
|
|
|
rst => rstn,
|
|
|
clk => clkm,
|
|
|
apbi => apbi,
|
|
|
apbo => apbo(8),
|
|
|
sample_clk_out => sample_clk_out,
|
|
|
GOtest => Test(1),
|
|
|
CoefsInitVal => (others => '1')
|
|
|
);
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- Reset and Clock generation -------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
vcc <= (others => '1'); gnd <= (others => '0');
|
|
|
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
|
|
|
|
|
|
rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
|
|
|
|
|
|
|
|
|
clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
|
|
|
|
|
|
clkgen0 : clkgen -- clock generator
|
|
|
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
|
|
|
CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
|
|
|
port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
|
|
|
|
|
|
ramclk <= clkm;
|
|
|
process(lclk2x)
|
|
|
begin
|
|
|
if lclk2x'event and lclk2x = '1' then
|
|
|
lclk <= not lclk;
|
|
|
end if;
|
|
|
end process;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- LEON3 processor / DSU / IRQ ------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
l3 : if CFG_LEON3 = 1 generate
|
|
|
cpu : for i in 0 to CFG_NCPU-1 generate
|
|
|
u0 : leon3s -- LEON3 processor
|
|
|
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
|
|
|
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
|
|
|
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
|
|
|
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
|
|
|
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
|
|
|
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
|
|
|
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
|
|
|
irqi(i), irqo(i), dbgi(i), dbgo(i));
|
|
|
end generate;
|
|
|
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
|
|
|
|
|
|
dsugen : if CFG_DSU = 1 generate
|
|
|
dsu0 : dsu3 -- LEON3 Debug Support Unit
|
|
|
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
|
|
|
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
|
|
|
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
|
|
|
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
|
|
|
dsui.enable <= '1';
|
|
|
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
|
|
|
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
|
|
|
end generate;
|
|
|
end generate;
|
|
|
|
|
|
nodsu : if CFG_DSU = 0 generate
|
|
|
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
|
|
|
end generate;
|
|
|
|
|
|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
|
|
|
irqctrl0 : irqmp -- interrupt controller
|
|
|
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
|
|
|
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
|
|
|
end generate;
|
|
|
irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
|
|
x : for i in 0 to CFG_NCPU-1 generate
|
|
|
irqi(i).irl <= "0000";
|
|
|
end generate;
|
|
|
apbo(2) <= apb_none;
|
|
|
end generate;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- Memory controllers ---------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
|
|
|
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
|
|
|
|
|
|
memi.brdyn <= '1'; memi.bexcn <= '1';
|
|
|
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
|
|
|
|
|
|
bdr : for i in 0 to 3 generate
|
|
|
data_pad : iopadv generic map (tech => padtech, width => 8)
|
|
|
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
|
|
|
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
|
|
|
end generate;
|
|
|
|
|
|
|
|
|
addr_pad : outpadv generic map (width => 19, tech => padtech)
|
|
|
port map (address, memo.address(20 downto 2));
|
|
|
|
|
|
|
|
|
SSRAM_0:entity ssram_plugin
|
|
|
generic map (tech => padtech)
|
|
|
port map
|
|
|
(lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- AHB CONTROLLER -------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
ahb0 : ahbctrl -- AHB arbiter/multiplexer
|
|
|
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
|
|
|
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
|
|
|
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
|
|
|
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- AHB UART -------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
dcomgen : if CFG_AHB_UART = 1 generate
|
|
|
dcom0: ahbuart -- Debug UART
|
|
|
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
|
|
|
port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
|
|
|
dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
|
|
|
dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
|
|
|
-- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
|
|
|
end generate;
|
|
|
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- APB Bridge -----------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
apb0 : apbctrl -- AHB/APB bridge
|
|
|
generic map (hindex => 1, haddr => CFG_APBADDR)
|
|
|
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- GPT Timer ------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
|
|
timer0 : gptimer -- timer unit
|
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
|
|
nbits => CFG_GPT_TW)
|
|
|
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
|
|
|
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
|
|
|
-- led(4) <= gpto.wdog;
|
|
|
end generate;
|
|
|
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
|
|
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- APB UART -------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
|
|
uart1 : apbuart -- UART 1
|
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
|
|
fifosize => CFG_UART1_FIFO)
|
|
|
port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
|
|
|
apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
|
|
|
apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
|
|
|
-- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
|
|
|
end generate;
|
|
|
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- GPIO -----------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
|
|
|
grgpio0: grgpio
|
|
|
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
|
|
|
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
|
|
|
|
|
|
pio_pads : for i in 0 to 6 generate
|
|
|
pio_pad : iopad generic map (tech => padtech)
|
|
|
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
|
|
|
end generate;
|
|
|
end generate;
|
|
|
|
|
|
|
|
|
end Behavioral;
|
