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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2012, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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library techmap;
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use techmap.gencomp.all;
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use work.debug.all;
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library hynix;
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use hynix.components.all;
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library micron;
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use work.config.all; -- configuration
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sramfile : string := "sram.srec"; -- ram contents
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constant sdramfile : string := "sdram.srec"; -- sdram contents
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signal clk : std_logic := '0';
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signal Rst : std_logic := '0'; -- Reset
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constant ct : integer := 40;
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signal address : std_logic_vector(24 downto 0);
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signal data : std_logic_vector(15 downto 0);
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signal button : std_logic_vector(3 downto 0) := "0000";
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signal genio : std_logic_vector(59 downto 0);
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signal romsn : std_logic;
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signal oen : std_ulogic;
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signal writen : std_ulogic;
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signal GND : std_ulogic := '0';
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signal VCC : std_ulogic := '1';
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signal NC : std_ulogic := 'Z';
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signal txd1, rxd1 : std_logic;
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signal txd2, rxd2 : std_logic;
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signal ctsn1, rtsn1 : std_ulogic;
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signal ctsn2, rtsn2 : std_ulogic;
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signal phy_mii_data: std_logic; -- ethernet PHY interface
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signal phy_tx_clk : std_ulogic;
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signal phy_rx_clk : std_ulogic;
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signal phy_rx_data : std_logic_vector(7 downto 0);
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signal phy_dv : std_ulogic;
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signal phy_rx_er : std_ulogic;
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signal phy_col : std_ulogic;
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signal phy_crs : std_ulogic;
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signal phy_tx_data : std_logic_vector(7 downto 0);
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signal phy_tx_en : std_ulogic;
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signal phy_tx_er : std_ulogic;
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signal phy_mii_clk : std_ulogic;
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signal phy_rst_n : std_ulogic;
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signal phy_gtx_clk : std_ulogic;
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signal phy_mii_int_n : std_ulogic;
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signal clk27 : std_ulogic := '0';
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signal clk200p : std_ulogic := '0';
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signal clk200n : std_ulogic := '1';
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signal clk33 : std_ulogic := '0';
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signal iic_scl : std_ulogic;
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signal iic_sda : std_ulogic;
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signal ddc_scl : std_ulogic;
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signal ddc_sda : std_ulogic;
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signal dvi_iic_scl : std_logic;
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signal dvi_iic_sda : std_logic;
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signal tft_lcd_data : std_logic_vector(11 downto 0);
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signal tft_lcd_clk_p : std_ulogic;
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signal tft_lcd_clk_n : std_ulogic;
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signal tft_lcd_hsync : std_ulogic;
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signal tft_lcd_vsync : std_ulogic;
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signal tft_lcd_de : std_ulogic;
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signal tft_lcd_reset_b : std_ulogic;
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-- DDR2 memory
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signal ddr_clk : std_logic;
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signal ddr_clkb : std_logic;
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signal ddr_clk_fb : std_logic;
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signal ddr_cke : std_logic;
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signal ddr_csb : std_logic := '0';
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signal ddr_we : std_ulogic; -- write enable
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signal ddr_ras : std_ulogic; -- ras
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signal ddr_cas : std_ulogic; -- cas
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signal ddr_dm : std_logic_vector(1 downto 0); -- dm
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signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
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signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
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signal ddr3_tdqs_n : std_logic_vector(1 downto 0); -- dqsn
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signal ddr_ad : std_logic_vector(12 downto 0); -- address
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signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
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signal ddr_dq : std_logic_vector(15 downto 0); -- data
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signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
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signal ddr_odt : std_logic;
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signal ddr_reset_n: std_logic;
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signal ddr_rzq : std_logic;
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signal ddr_zio : std_logic;
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-- SPI flash
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signal spi_sel_n : std_ulogic;
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signal spi_clk : std_ulogic;
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signal spi_mosi : std_ulogic;
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signal dsurst : std_ulogic;
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signal errorn : std_logic;
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signal switch : std_logic_vector(3 downto 0); -- I/O port
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signal led : std_logic_vector(3 downto 0); -- I/O port
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constant lresp : boolean := false;
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begin
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-- clock and reset
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clk27 <= not clk27 after ct * 1 ns;
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clk33 <= not clk33 after 15 ns;
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clk200p <= not clk200p after 2.5 ns;
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clk200n <= not clk200n after 2.5 ns;
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rst <= not dsurst;
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rxd1 <= 'H'; ctsn1 <= '0';
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rxd2 <= 'H'; ctsn2 <= '0';
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button <= "0000";
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switch <= "0000";
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cpu : entity work.leon3mp
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generic map ( fabtech, memtech, padtech, clktech,
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disas, dbguart, pclow )
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port map (rst, clk27, clk200p, clk200n, clk33, address(24 downto 1),
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data, oen, writen, romsn,
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ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_reset_n, ddr_we, ddr_ras, ddr_cas, ddr_dm,
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ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
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txd1, rxd1, ctsn1, rtsn1, button,
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switch, led,
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phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
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phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data,
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phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_mii_int_n,
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iic_scl, iic_sda, ddc_scl, ddc_sda,
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dvi_iic_scl, dvi_iic_sda,
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tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
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tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
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spi_sel_n, spi_clk, spi_mosi
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);
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-- prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
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-- port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
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-- writen, oen);
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prom0 : for i in 0 to 1 generate
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sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
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port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
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writen, oen);
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end generate;
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address(0) <= '0';
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u1 : entity micron.ddr3
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port map ( rst_n => ddr_reset_n, dq => ddr_dq,
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tdqs_n => ddr3_tdqs_n,
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dqs => ddr_dqs, dqs_n => ddr_dqsn,
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dm_tdqs => ddr_dm, we_n => ddr_we, cas_n => ddr_cas,
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ras_n => ddr_ras, cs_n => ddr_csb, ba => ddr_ba,
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addr => ddr_ad(12 downto 0), cke => ddr_cke,
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ck => ddr_clk, ck_n => ddr_clkb, odt => ddr_odt) ;
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errorn <= led(1);
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errorn <= 'H'; -- ERROR pull-up
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phy0 : if (CFG_GRETH = 1) generate
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phy_mii_data <= 'H';
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p0: phy
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generic map (address => 7)
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port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
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phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
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phy_tx_er, phy_mii_clk, phy_gtx_clk);
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end generate;
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iuerr : process
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begin
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wait for 5000 ns;
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if to_x01(errorn) = '1' then wait on errorn; end if;
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assert (to_x01(errorn) = '1')
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report "*** IU in error mode, simulation halted ***"
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severity failure ;
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end process;
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data <= buskeep(data) after 5 ns;
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dsucom : process
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procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
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variable w32 : std_logic_vector(31 downto 0);
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variable c8 : std_logic_vector(7 downto 0);
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constant txp : time := 320 * 1 ns;
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begin
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dsutx <= '1';
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dsurst <= '0';
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wait for 2500 ns;
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dsurst <= '1';
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wait;
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wait for 5000 ns;
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txc(dsutx, 16#55#, txp); -- sync uart
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
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wait for 25000 ns;
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
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txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
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txc(dsutx, 16#80#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
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wait;
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
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txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
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txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
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txc(dsutx, 16#80#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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rxi(dsurx, w32, txp, lresp);
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txc(dsutx, 16#a0#, txp);
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txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
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rxi(dsurx, w32, txp, lresp);
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end;
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begin
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dsucfg(txd2, rxd2);
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wait;
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end process;
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end ;
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