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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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entity TopMatrix_PDR is
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generic(
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Input_SZ : integer := 16);
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port(
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clk : in std_logic;
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reset : in std_logic;
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Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
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FULLin : in std_logic_vector(4 downto 0);
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READin : in std_logic_vector(1 downto 0);
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WRITEin : in std_logic;
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FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
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FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
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Start : out std_logic;
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Read : out std_logic_vector(4 downto 0);
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Statu : out std_logic_vector(3 downto 0)
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);
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end entity;
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architecture ar_TopMatrix_PDR of TopMatrix_PDR is
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type state is (st0,st1,st2,st3);
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signal ect : state;
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signal i,j : integer;
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signal full_int : std_logic_vector(1 downto 0);
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signal WRITEin_reg : std_logic;
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begin
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process(clk,reset)
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begin
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if(reset='0')then
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i <= 1;
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j <= 0;
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Start <= '0';
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WRITEin_reg <= '0';
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ect <= st0;
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elsif(clk'event and clk='1')then
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WRITEin_reg <= WRITEin;
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case ect is
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when st0 =>
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if(full_int = "11")then
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Start <= '1';
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ect <= st1;
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end if;
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when st1 =>
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if(WRITEin_reg='1' and WRITEin='0')then
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if(i=1 or i=3 or i=6 or i=10 or i=15)then
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ect <= st2;
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else
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ect <= st3;
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end if;
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end if;
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when st2 =>
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if(j=127)then
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if(i=15)then
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i <= 1;
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else
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i <= i+1;
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end if;
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j <= 0;
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Start <= '0';
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ect <= st0;
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elsif(WRITEin_reg='1' and WRITEin='0')then
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j <= j+1;
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end if;
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when st3 =>
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if(j=255)then
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j <= 0;
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i <= i+1;
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Start <= '0';
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ect <= st0;
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elsif(WRITEin_reg='1' and WRITEin='0')then
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j <= j+1;
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end if;
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end case;
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end if;
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end process;
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Statu <= std_logic_vector(to_unsigned(i,4));
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with i select
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FIFO1 <= Data(15 downto 0) when 1,
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Data(15 downto 0) when 2,
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Data(31 downto 16) when 3,
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Data(15 downto 0) when 4,
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Data(31 downto 16) when 5,
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Data(47 downto 32) when 6,
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Data(15 downto 0) when 7,
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Data(31 downto 16) when 8,
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Data(47 downto 32) when 9,
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Data(63 downto 48) when 10,
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Data(15 downto 0) when 11,
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Data(31 downto 16) when 12,
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Data(47 downto 32) when 13,
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Data(63 downto 48) when 14,
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Data(79 downto 64) when 15,
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X"0000" when others;
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with i select
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FIFO2 <= (others => '0') when 1,
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Data(31 downto 16) when 2,
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(others => '0') when 3,
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Data(47 downto 32) when 4,
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Data(47 downto 32) when 5,
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(others => '0') when 6,
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Data(63 downto 48) when 7,
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Data(63 downto 48) when 8,
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Data(63 downto 48) when 9,
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(others => '0') when 10,
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Data(79 downto 64) when 11,
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Data(79 downto 64) when 12,
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Data(79 downto 64) when 13,
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Data(79 downto 64) when 14,
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(others => '0') when 15,
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X"0000" when others;
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with i select
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Read <= "1111" & not READin(0) when 1,
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"111" & not READin(1) & not READin(0) when 2,
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"111" & not READin(0) & '1' when 3,
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"11" & not READin(1) & '1' & not READin(0) when 4,
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"11" & not READin(1) & not READin(0) & '1' when 5,
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"11" & not READin(0) & "11" when 6,
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"1" & not READin(1) & "11" & not READin(0) when 7,
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'1' & not READin(1) & '1' & not READin(0) & '1' when 8,
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'1' & not READin(1) & not READin(0) & "11" when 9,
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'1' & not READin(0) & "111" when 10,
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not READin(1) & "111" & not READin(0) when 11,
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not READin(1) & "11" & not READin(0) & '1' when 12,
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not READin(1) & '1' & not READin(0) & "11" when 13,
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not READin(1) & not READin(0) & "111" when 14,
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not READin(0) & "1111" when 15,
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"11111" when others;
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with i select
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full_int <= FULLin(0) & FULLin(0) when 1,
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FULLin(1) & FULLin(0) when 2,
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FULLin(1) & FULLin(1) when 3,
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FULLin(2) & FULLin(0) when 4,
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FULLin(2) & FULLin(1) when 5,
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FULLin(2) & FULLin(2) when 6,
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FULLin(3) & FULLin(0) when 7,
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FULLin(3) & FULLin(1) when 8,
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FULLin(3) & FULLin(2) when 9,
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FULLin(3) & FULLin(3) when 10,
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FULLin(4) & FULLin(0) when 11,
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FULLin(4) & FULLin(1) when 12,
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FULLin(4) & FULLin(2) when 13,
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FULLin(4) & FULLin(3) when 14,
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FULLin(4) & FULLin(4) when 15,
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"00" when others;
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end architecture;
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