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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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PACKAGE lpp_waveform_pkg IS
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TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
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TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
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-----------------------------------------------------------------------------
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-- SNAPSHOT
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-----------------------------------------------------------------------------
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COMPONENT lpp_waveform_snapshot
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GENERIC (
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data_size : INTEGER;
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nb_snapshot_param_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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enable : IN STD_LOGIC;
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burst_enable : IN STD_LOGIC;
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nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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start_snapshot : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_burst
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GENERIC (
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data_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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enable : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_snapshot_controler
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GENERIC (
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delta_vector_size : INTEGER;
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delta_vector_size_f0_2 : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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reg_run : IN STD_LOGIC;
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reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
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reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
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data_f0_valid : IN STD_LOGIC;
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data_f2_valid : IN STD_LOGIC;
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start_snapshot_f0 : OUT STD_LOGIC;
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start_snapshot_f1 : OUT STD_LOGIC;
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start_snapshot_f2 : OUT STD_LOGIC;
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wfp_on : OUT STD_LOGIC);
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END COMPONENT;
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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COMPONENT lpp_waveform
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GENERIC (
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tech : INTEGER;
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data_size : INTEGER;
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nb_data_by_buffer_size : INTEGER;
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nb_snapshot_param_size : INTEGER;
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delta_vector_size : INTEGER;
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delta_vector_size_f0_2 : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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reg_run : IN STD_LOGIC;
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reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
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reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
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reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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enable_f0 : IN STD_LOGIC;
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enable_f1 : IN STD_LOGIC;
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enable_f2 : IN STD_LOGIC;
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enable_f3 : IN STD_LOGIC;
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burst_f0 : IN STD_LOGIC;
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burst_f1 : IN STD_LOGIC;
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burst_f2 : IN STD_LOGIC;
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nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
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nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
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status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
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length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
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ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
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error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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--fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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data_f0_in_valid : IN STD_LOGIC;
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data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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data_f1_in_valid : IN STD_LOGIC;
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data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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data_f2_in_valid : IN STD_LOGIC;
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data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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data_f3_in_valid : IN STD_LOGIC;
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data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
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dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
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dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
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dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT lpp_waveform_dma_genvalid
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PORT (
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HCLK : IN STD_LOGIC;
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HRESETn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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valid_in : IN STD_LOGIC;
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ack_in : IN STD_LOGIC;
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time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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valid_out : OUT STD_LOGIC;
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time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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error : OUT STD_LOGIC);
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END COMPONENT;
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-----------------------------------------------------------------------------
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-- FIFO
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-----------------------------------------------------------------------------
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COMPONENT lpp_waveform_fifo_ctrl
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GENERIC (
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offset : INTEGER;
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length : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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ren : IN STD_LOGIC;
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wen : IN STD_LOGIC;
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mem_re : OUT STD_LOGIC;
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mem_we : OUT STD_LOGIC;
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mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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empty_almost : OUT STD_LOGIC;
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empty : OUT STD_LOGIC;
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full_almost : OUT STD_LOGIC;
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full : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_waveform_fifo_arbiter
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GENERIC (
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tech : INTEGER;
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nb_data_by_buffer_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
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time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
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data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT lpp_waveform_fifo
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GENERIC (
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tech : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_waveform_fifo_headreg
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GENERIC (
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tech : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_waveform_fifo_latencyCorrection
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GENERIC (
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tech : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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empty_almost : OUT STD_LOGIC;
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empty : OUT STD_LOGIC;
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data_ren : IN STD_LOGIC;
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rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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empty_almost_fifo : IN STD_LOGIC;
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empty_fifo : IN STD_LOGIC;
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data_ren_fifo : OUT STD_LOGIC;
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rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_waveform_fifo_withoutLatency
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GENERIC (
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tech : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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-----------------------------------------------------------------------------
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-- GEN ADDRESS
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-----------------------------------------------------------------------------
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COMPONENT lpp_waveform_genaddress
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GENERIC (
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nb_data_by_buffer_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
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addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_f0_data_out_valid_burst : OUT STD_LOGIC;
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data_f1_data_out_valid_burst : OUT STD_LOGIC;
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data_f2_data_out_valid_burst : OUT STD_LOGIC;
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data_f3_data_out_valid_burst : OUT STD_LOGIC;
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data_f0_data_out_valid : OUT STD_LOGIC;
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data_f1_data_out_valid : OUT STD_LOGIC;
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data_f2_data_out_valid : OUT STD_LOGIC;
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data_f3_data_out_valid : OUT STD_LOGIC;
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data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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-----------------------------------------------------------------------------
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-- lpp_waveform_fifo_arbiter_reg
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-----------------------------------------------------------------------------
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COMPONENT lpp_waveform_fifo_arbiter_reg
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GENERIC (
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data_size : INTEGER;
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data_nb : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
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enable : IN STD_LOGIC;
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sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
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data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
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data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT lpp_waveform_fsmdma
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PORT (
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clk : IN STD_ULOGIC;
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rstn : IN STD_ULOGIC;
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run : IN STD_LOGIC;
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fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_empty_threshold : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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dma_fifo_valid_burst : OUT STD_LOGIC;
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dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_fifo_ren : IN STD_LOGIC;
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dma_buffer_new : OUT STD_LOGIC;
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dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
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dma_buffer_full : IN STD_LOGIC;
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dma_buffer_full_err : IN STD_LOGIC;
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status_buffer_ready : IN STD_LOGIC;
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addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
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ready_buffer : OUT STD_LOGIC;
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buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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error_buffer_full : OUT STD_LOGIC);
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END COMPONENT;
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END lpp_waveform_pkg;
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