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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_top_lfr_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_top_acq IS
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GENERIC(
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tech : INTEGER := 0
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);
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PORT (
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-- ADS7886
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cnv_run : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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sck : OUT STD_LOGIC;
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sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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--
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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--
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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--
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sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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--
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sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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--
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sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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--
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sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)
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);
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END lpp_top_acq;
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ARCHITECTURE tb OF lpp_top_acq IS
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COMPONENT Downsampling
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GENERIC (
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ChanelCount : INTEGER;
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SampleSize : INTEGER;
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DivideParam : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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sample_in_val : IN STD_LOGIC;
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sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
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sample_out_val : OUT STD_LOGIC;
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sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
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END COMPONENT;
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-----------------------------------------------------------------------------
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CONSTANT ChanelCount : INTEGER := 8;
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CONSTANT ncycle_cnv_high : INTEGER := 79;
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CONSTANT ncycle_cnv : INTEGER := 500;
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-----------------------------------------------------------------------------
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SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL sample_val_delay : STD_LOGIC;
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-----------------------------------------------------------------------------
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CONSTANT Coef_SZ : INTEGER := 9;
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CONSTANT CoefCntPerCel : INTEGER := 6;
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CONSTANT CoefPerCel : INTEGER := 5;
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CONSTANT Cels_count : INTEGER := 5;
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-- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
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SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
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SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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-- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--
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SIGNAL sample_filter_JC_out_val : STD_LOGIC;
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SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--
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SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
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SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL sample_downsampling_out_val : STD_LOGIC;
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SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--
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SIGNAL sample_f0_val : STD_LOGIC;
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SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--
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SIGNAL sample_f0_0_val : STD_LOGIC;
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SIGNAL sample_f0_1_val : STD_LOGIC;
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SIGNAL counter_f0 : INTEGER;
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-----------------------------------------------------------------------------
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SIGNAL sample_f1_val : STD_LOGIC;
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SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--
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SIGNAL sample_f2_val : STD_LOGIC;
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SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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--
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SIGNAL sample_f3_val : STD_LOGIC;
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SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
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BEGIN
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-- component instantiation
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-----------------------------------------------------------------------------
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DIGITAL_acquisition : ADS7886_drvr
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GENERIC MAP (
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ChanelCount => ChanelCount,
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ncycle_cnv_high => ncycle_cnv_high,
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ncycle_cnv => ncycle_cnv)
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PORT MAP (
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cnv_clk => cnv_clk, --
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cnv_rstn => cnv_rstn, --
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cnv_run => cnv_run, --
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cnv => cnv, --
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clk => clk, --
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rstn => rstn, --
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sck => sck, --
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sdo => sdo(ChanelCount-1 DOWNTO 0), --
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sample => sample,
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sample_val => sample_val);
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_val_delay <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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sample_val_delay <= sample_val;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
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SampleLoop : FOR j IN 0 TO 15 GENERATE
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sample_filter_in(i, j) <= sample(i)(j);
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END GENERATE;
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sample_filter_in(i, 16) <= sample(i)(15);
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sample_filter_in(i, 17) <= sample(i)(15);
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END GENERATE;
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-- coefs <= CoefsInitValCst;
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coefs_JC <= CoefsInitValCst_JC;
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--FILTER : IIR_CEL_CTRLR
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-- GENERIC MAP (
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-- tech => 0,
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-- Sample_SZ => 18,
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-- ChanelsCount => ChanelCount,
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-- Coef_SZ => Coef_SZ,
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-- CoefCntPerCel => CoefCntPerCel,
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-- Cels_count => Cels_count,
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-- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
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-- PORT MAP (
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-- reset => rstn,
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-- clk => clk,
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-- sample_clk => sample_val_delay,
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-- sample_in => sample_filter_in,
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-- sample_out => sample_filter_out,
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-- virg_pos => 7,
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-- GOtest => OPEN,
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-- coefs => coefs);
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IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
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GENERIC MAP (
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tech => 0,
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Mem_use => use_CEL,
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Sample_SZ => 18,
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Coef_SZ => Coef_SZ,
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Coef_Nb => 25, -- TODO
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Coef_sel_SZ => 5, -- TODO
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Cels_count => Cels_count,
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ChanelsCount => ChanelCount)
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PORT MAP (
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rstn => rstn,
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clk => clk,
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virg_pos => 7,
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coefs => coefs_JC,
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sample_in_val => sample_val_delay,
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sample_in => sample_filter_in,
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sample_out_val => sample_filter_JC_out_val,
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sample_out => sample_filter_JC_out);
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_filter_JC_out_r_val <= '0';
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rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
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rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
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sample_filter_JC_out_r(I, J) <= '0';
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END LOOP rst_all_bits;
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END LOOP rst_all_chanel;
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
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IF sample_filter_JC_out_val = '1' THEN
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sample_filter_JC_out_r <= sample_filter_JC_out;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- F0 -- @24.576 kHz
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-----------------------------------------------------------------------------
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Downsampling_f0 : Downsampling
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GENERIC MAP (
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ChanelCount => ChanelCount,
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SampleSize => 18,
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DivideParam => 4)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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sample_in_val => sample_filter_JC_out_val ,
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sample_in => sample_filter_JC_out,
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sample_out_val => sample_f0_val,
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sample_out => sample_f0);
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all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE
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sample_f0_wdata(I) <= sample_f0(0, I);
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sample_f0_wdata(18*1+I) <= sample_f0(1, I);
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sample_f0_wdata(18*2+I) <= sample_f0(2, I);
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sample_f0_wdata(18*3+I) <= sample_f0(6, I);
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sample_f0_wdata(18*4+I) <= sample_f0(7, I);
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END GENERATE all_bit_sample_f0;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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counter_f0 <= 0;
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF sample_f0_val = '1' THEN
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IF counter_f0 = 511 THEN
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counter_f0 <= 0;
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ELSE
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counter_f0 <= counter_f0 + 1;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
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sample_f0_0_wen <= NOT(sample_f0_0_val) &
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NOT(sample_f0_0_val) &
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NOT(sample_f0_0_val) &
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NOT(sample_f0_0_val) &
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NOT(sample_f0_0_val);
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sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
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sample_f0_1_wen <= NOT(sample_f0_1_val) &
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NOT(sample_f0_1_val) &
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NOT(sample_f0_1_val) &
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NOT(sample_f0_1_val) &
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NOT(sample_f0_1_val);
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-----------------------------------------------------------------------------
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-- F1 -- @4096 Hz
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-----------------------------------------------------------------------------
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Downsampling_f1 : Downsampling
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GENERIC MAP (
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ChanelCount => ChanelCount,
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SampleSize => 18,
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DivideParam => 6)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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sample_in_val => sample_f0_val ,
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sample_in => sample_f0,
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sample_out_val => sample_f1_val,
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sample_out => sample_f1);
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sample_f1_wen <= NOT(sample_f1_val) &
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NOT(sample_f1_val) &
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NOT(sample_f1_val) &
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NOT(sample_f1_val) &
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NOT(sample_f1_val);
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all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE
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sample_f1_wdata(I) <= sample_f1(0, I);
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sample_f1_wdata(18*1+I) <= sample_f1(1, I);
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sample_f1_wdata(18*2+I) <= sample_f1(2, I);
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sample_f1_wdata(18*3+I) <= sample_f1(6, I);
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sample_f1_wdata(18*4+I) <= sample_f1(7, I);
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END GENERATE all_bit_sample_f1;
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-----------------------------------------------------------------------------
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-- F2 -- @16 Hz
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-----------------------------------------------------------------------------
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Downsampling_f2 : Downsampling
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GENERIC MAP (
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ChanelCount => ChanelCount,
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SampleSize => 18,
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DivideParam => 256)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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sample_in_val => sample_f1_val ,
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sample_in => sample_f1,
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sample_out_val => sample_f2_val,
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sample_out => sample_f2);
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sample_f2_wen <= NOT(sample_f2_val) &
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NOT(sample_f2_val) &
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NOT(sample_f2_val) &
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NOT(sample_f2_val) &
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NOT(sample_f2_val);
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all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE
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sample_f2_wdata(I) <= sample_f2(0, I);
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sample_f2_wdata(18*1+I) <= sample_f2(1, I);
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sample_f2_wdata(18*2+I) <= sample_f2(2, I);
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sample_f2_wdata(18*3+I) <= sample_f2(6, I);
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sample_f2_wdata(18*4+I) <= sample_f2(7, I);
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END GENERATE all_bit_sample_f2;
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-----------------------------------------------------------------------------
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-- F3 -- @256 Hz
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-----------------------------------------------------------------------------
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Downsampling_f3 : Downsampling
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GENERIC MAP (
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ChanelCount => ChanelCount,
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SampleSize => 18,
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DivideParam => 96)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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sample_in_val => sample_f0_val ,
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sample_in => sample_f0,
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sample_out_val => sample_f3_val,
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sample_out => sample_f3);
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sample_f3_wen <= (NOT sample_f3_val) &
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(NOT sample_f3_val) &
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(NOT sample_f3_val) &
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(NOT sample_f3_val) &
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(NOT sample_f3_val);
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all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE
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sample_f3_wdata(I) <= sample_f3(0, I);
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sample_f3_wdata(18*1+I) <= sample_f3(1, I);
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sample_f3_wdata(18*2+I) <= sample_f3(2, I);
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sample_f3_wdata(18*3+I) <= sample_f3(6, I);
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sample_f3_wdata(18*4+I) <= sample_f3(7, I);
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END GENERATE all_bit_sample_f3;
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END tb;
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