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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.general_purpose.Clk_divider;
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entity AD7688_drvr is
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generic(ChanelCount : integer;
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clkkHz : integer);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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smplClk: in STD_LOGIC;
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DataReady : out std_logic;
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smpout : out Samples_out(ChanelCount-1 downto 0);
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AD_in : in AD7688_in(ChanelCount-1 downto 0);
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AD_out : out AD7688_out);
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end AD7688_drvr;
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architecture ar_AD7688_drvr of AD7688_drvr is
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constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs
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signal i : integer range 0 to convTrigger :=0;
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signal clk_int : std_logic;
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signal smplClk_reg : std_logic;
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signal cnv_int : std_logic;
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begin
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clkdiv: if clkkHz>=66000 generate
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clkdivider: Clk_divider
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generic map(clkkHz*1000,60000000)
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Port map( clk ,reset,clk_int);
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end generate;
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clknodiv: if clkkHz<66000 generate
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nodiv: clk_int <= clk;
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end generate;
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AD_out.CNV <= cnv_int;
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AD_out.SCK <= clk_int;
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sckgen: process(clk,reset)
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begin
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if reset = '0' then
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i <= 0;
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cnv_int <= '0';
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smplClk_reg <= '0';
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elsif clk'event and clk = '1' then
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if smplClk = '1' and smplClk_reg = '0' then
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if i = convTrigger then
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smplClk_reg <= '1';
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i <= 0;
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cnv_int <= '0';
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else
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i <= i+1;
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cnv_int <= '1';
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end if;
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elsif smplClk = '0' and smplClk_reg = '1' then
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smplClk_reg <= '0';
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end if;
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end if;
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end process;
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spidrvr: AD7688_spi_if
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generic map(ChanelCount)
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Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout);
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end ar_AD7688_drvr;
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