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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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--! Programme qui va permettre de g�n�rer le signal SYNC
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entity Gene_SYNC is
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port(
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SysClk,raz : in std_logic; --! Horloge systeme et Reset du composant
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SCLK : in std_logic;
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enable : in std_logic; --! Autorise ou non l'utilisation du composant
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sended : in std_logic;
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send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
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Readn : out std_logic;
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SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
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);
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end Gene_SYNC;
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architecture ar_Gene_SYNC of Gene_SYNC is
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--signal count : integer;
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signal SysClk_reg : std_logic;
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type etat is (e0,e1,e2,e3);
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signal ect : etat;
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begin
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process (SCLK,raz)
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begin
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if(raz='0')then
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ect <= e0;
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SYNC <= '1';
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Readn <= '1';
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---- count <= 14;
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Send <= '0';
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elsif(SCLK' event and SCLK='1')then
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SysClk_reg <= SysClk;
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if(enable='1')then
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case ect is
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when e0 =>
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if(SysClk_reg='0' and SysClk='1')then
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-- SYNC <= '0';
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Readn <= '0';
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Send <= '1';
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ect <= e1;
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end if;
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when e1 =>
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Readn <= '1';
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-- SYNC <= '0';
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send <= '0';
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ect <= e2;
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when e2 =>
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SYNC <= '0';
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ect <= e3;
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when e3 =>
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if(sended='1')then
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SYNC <= '1';
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ect <= e0;
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end if;
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-- if(count=15)then
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-- SYNC <= '1';
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-- count <= count+1;
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-- if(Ready='1')then
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---- count <= 0;
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-- SYNC <= '1';
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--
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-- ect <= e0;
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---- count <= count+1;
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-- Send <= '0';
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-- end if;
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end case;
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end if;
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end if;
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end process;
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end ar_Gene_SYNC;
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