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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package spwcomp is
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component grspwc2 is
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generic(
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rmap : integer range 0 to 1 := 0;
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rmapcrc : integer range 0 to 1 := 0;
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fifosize1 : integer range 4 to 32 := 32;
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fifosize2 : integer range 16 to 64 := 64;
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rxunaligned : integer range 0 to 1 := 0;
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rmapbufs : integer range 2 to 8 := 4;
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scantest : integer range 0 to 1 := 0;
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ports : integer range 1 to 2 := 1;
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dmachan : integer range 1 to 4 := 1;
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tech : integer;
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input_type : integer range 0 to 3 := 0;
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output_type : integer range 0 to 2 := 0;
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rxtx_sameclk : integer range 0 to 1 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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rxclk0 : in std_ulogic;
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rxclk1 : in std_ulogic;
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txclk : in std_ulogic;
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txclkn : in std_ulogic;
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--ahb mst in
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hgrant : in std_ulogic;
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hready : in std_ulogic;
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hresp : in std_logic_vector(1 downto 0);
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hrdata : in std_logic_vector(31 downto 0);
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--ahb mst out
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hbusreq : out std_ulogic;
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hlock : out std_ulogic;
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htrans : out std_logic_vector(1 downto 0);
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haddr : out std_logic_vector(31 downto 0);
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hwrite : out std_ulogic;
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hsize : out std_logic_vector(2 downto 0);
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hburst : out std_logic_vector(2 downto 0);
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hprot : out std_logic_vector(3 downto 0);
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hwdata : out std_logic_vector(31 downto 0);
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--apb slv in
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psel : in std_ulogic;
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penable : in std_ulogic;
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paddr : in std_logic_vector(31 downto 0);
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pwrite : in std_ulogic;
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pwdata : in std_logic_vector(31 downto 0);
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--apb slv out
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prdata : out std_logic_vector(31 downto 0);
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--spw in
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d : in std_logic_vector(3 downto 0);
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dv : in std_logic_vector(3 downto 0);
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dconnect : in std_logic_vector(3 downto 0);
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--spw out
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do : out std_logic_vector(3 downto 0);
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so : out std_logic_vector(3 downto 0);
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--time iface
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tickin : in std_ulogic;
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tickinraw : in std_ulogic;
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timein : in std_logic_vector(7 downto 0);
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tickindone : out std_ulogic;
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tickout : out std_ulogic;
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tickoutraw : out std_ulogic;
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timeout : out std_logic_vector(7 downto 0);
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--irq
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irq : out std_logic;
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--misc
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clkdiv10 : in std_logic_vector(7 downto 0);
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--rmapen
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rmapen : in std_ulogic;
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--rx ahb fifo
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rxrenable : out std_ulogic;
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rxraddress : out std_logic_vector(4 downto 0);
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rxwrite : out std_ulogic;
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rxwdata : out std_logic_vector(31 downto 0);
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rxwaddress : out std_logic_vector(4 downto 0);
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rxrdata : in std_logic_vector(31 downto 0);
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--tx ahb fifo
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txrenable : out std_ulogic;
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txraddress : out std_logic_vector(4 downto 0);
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txwrite : out std_ulogic;
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txwdata : out std_logic_vector(31 downto 0);
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txwaddress : out std_logic_vector(4 downto 0);
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txrdata : in std_logic_vector(31 downto 0);
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--nchar fifo
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ncrenable : out std_ulogic;
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ncraddress : out std_logic_vector(5 downto 0);
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ncwrite : out std_ulogic;
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ncwdata : out std_logic_vector(9 downto 0);
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ncwaddress : out std_logic_vector(5 downto 0);
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ncrdata : in std_logic_vector(9 downto 0);
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--rmap buf
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rmrenable : out std_ulogic;
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rmraddress : out std_logic_vector(7 downto 0);
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rmwrite : out std_ulogic;
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rmwdata : out std_logic_vector(7 downto 0);
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rmwaddress : out std_logic_vector(7 downto 0);
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rmrdata : in std_logic_vector(7 downto 0);
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linkdis : out std_ulogic;
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testrst : in std_ulogic := '0';
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testen : in std_ulogic := '0';
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--parallel rx data out
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rxdav : out std_ulogic;
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rxdataout : out std_logic_vector(8 downto 0);
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loopback : out std_ulogic
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);
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end component;
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component grspwc is
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generic(
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sysfreq : integer := 40000;
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usegen : integer range 0 to 1 := 1;
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nsync : integer range 1 to 2 := 1;
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rmap : integer range 0 to 2 := 0;
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rmapcrc : integer range 0 to 1 := 0;
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fifosize1 : integer range 4 to 32 := 32;
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fifosize2 : integer range 16 to 64 := 64;
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rxunaligned : integer range 0 to 1 := 0;
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rmapbufs : integer range 2 to 8 := 4;
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scantest : integer range 0 to 1 := 0;
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ports : integer range 1 to 2 := 1;
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tech : integer;
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nodeaddr : integer range 0 to 255 := 254;
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destkey : integer range 0 to 255 := 0
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);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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txclk : in std_ulogic;
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--ahb mst in
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hgrant : in std_ulogic;
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hready : in std_ulogic;
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hresp : in std_logic_vector(1 downto 0);
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hrdata : in std_logic_vector(31 downto 0);
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--ahb mst out
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hbusreq : out std_ulogic;
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hlock : out std_ulogic;
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htrans : out std_logic_vector(1 downto 0);
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haddr : out std_logic_vector(31 downto 0);
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hwrite : out std_ulogic;
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hsize : out std_logic_vector(2 downto 0);
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hburst : out std_logic_vector(2 downto 0);
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hprot : out std_logic_vector(3 downto 0);
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hwdata : out std_logic_vector(31 downto 0);
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--apb slv in
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psel : in std_ulogic;
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penable : in std_ulogic;
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paddr : in std_logic_vector(31 downto 0);
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pwrite : in std_ulogic;
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pwdata : in std_logic_vector(31 downto 0);
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--apb slv out
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prdata : out std_logic_vector(31 downto 0);
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--spw in
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di : in std_logic_vector(1 downto 0);
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si : in std_logic_vector(1 downto 0);
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--spw out
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do : out std_logic_vector(1 downto 0);
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so : out std_logic_vector(1 downto 0);
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--time iface
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tickin : in std_ulogic;
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tickout : out std_ulogic;
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--irq
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irq : out std_logic;
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--misc
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clkdiv10 : in std_logic_vector(7 downto 0);
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dcrstval : in std_logic_vector(9 downto 0);
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timerrstval : in std_logic_vector(11 downto 0);
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--rmapen
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rmapen : in std_ulogic;
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--clk bufs
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rxclki : in std_logic_vector(1 downto 0);
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nrxclki : in std_logic_vector(1 downto 0);
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rxclko : out std_logic_vector(1 downto 0);
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--rx ahb fifo
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rxrenable : out std_ulogic;
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rxraddress : out std_logic_vector(4 downto 0);
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rxwrite : out std_ulogic;
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rxwdata : out std_logic_vector(31 downto 0);
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rxwaddress : out std_logic_vector(4 downto 0);
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rxrdata : in std_logic_vector(31 downto 0);
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--tx ahb fifo
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txrenable : out std_ulogic;
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txraddress : out std_logic_vector(4 downto 0);
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txwrite : out std_ulogic;
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txwdata : out std_logic_vector(31 downto 0);
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txwaddress : out std_logic_vector(4 downto 0);
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txrdata : in std_logic_vector(31 downto 0);
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--nchar fifo
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ncrenable : out std_ulogic;
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ncraddress : out std_logic_vector(5 downto 0);
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ncwrite : out std_ulogic;
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ncwdata : out std_logic_vector(8 downto 0);
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ncwaddress : out std_logic_vector(5 downto 0);
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ncrdata : in std_logic_vector(8 downto 0);
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--rmap buf
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rmrenable : out std_ulogic;
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rmraddress : out std_logic_vector(7 downto 0);
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rmwrite : out std_ulogic;
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rmwdata : out std_logic_vector(7 downto 0);
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rmwaddress : out std_logic_vector(7 downto 0);
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rmrdata : in std_logic_vector(7 downto 0);
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linkdis : out std_ulogic;
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testclk : in std_ulogic := '0';
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testrst : in std_ulogic := '0';
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testen : in std_ulogic := '0';
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rmapact : out std_ulogic
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);
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end component;
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component grspwc_axcelerator is
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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txclk : in std_ulogic;
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--ahb mst in
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hgrant : in std_ulogic;
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hready : in std_ulogic;
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hresp : in std_logic_vector(1 downto 0);
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hrdata : in std_logic_vector(31 downto 0);
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--ahb mst out
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hbusreq : out std_ulogic;
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hlock : out std_ulogic;
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htrans : out std_logic_vector(1 downto 0);
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haddr : out std_logic_vector(31 downto 0);
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hwrite : out std_ulogic;
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hsize : out std_logic_vector(2 downto 0);
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hburst : out std_logic_vector(2 downto 0);
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hprot : out std_logic_vector(3 downto 0);
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hwdata : out std_logic_vector(31 downto 0);
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--apb slv in
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psel : in std_ulogic;
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penable : in std_ulogic;
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paddr : in std_logic_vector(31 downto 0);
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pwrite : in std_ulogic;
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pwdata : in std_logic_vector(31 downto 0);
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--apb slv out
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prdata : out std_logic_vector(31 downto 0);
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--spw in
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di : in std_logic_vector(1 downto 0);
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si : in std_logic_vector(1 downto 0);
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--spw out
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do : out std_logic_vector(1 downto 0);
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so : out std_logic_vector(1 downto 0);
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--time iface
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tickin : in std_ulogic;
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tickout : out std_ulogic;
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--irq
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irq : out std_logic;
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--misc
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clkdiv10 : in std_logic_vector(7 downto 0);
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dcrstval : in std_logic_vector(9 downto 0);
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timerrstval : in std_logic_vector(11 downto 0);
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--rmapen
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rmapen : in std_ulogic;
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--clk bufs
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rxclki : in std_logic_vector(1 downto 0);
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nrxclki : in std_logic_vector(1 downto 0);
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rxclko : out std_logic_vector(1 downto 0);
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--rx ahb fifo
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rxrenable : out std_ulogic;
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rxraddress : out std_logic_vector(4 downto 0);
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rxwrite : out std_ulogic;
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rxwdata : out std_logic_vector(31 downto 0);
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rxwaddress : out std_logic_vector(4 downto 0);
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rxrdata : in std_logic_vector(31 downto 0);
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--tx ahb fifo
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txrenable : out std_ulogic;
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txraddress : out std_logic_vector(4 downto 0);
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txwrite : out std_ulogic;
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txwdata : out std_logic_vector(31 downto 0);
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txwaddress : out std_logic_vector(4 downto 0);
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txrdata : in std_logic_vector(31 downto 0);
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--nchar fifo
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ncrenable : out std_ulogic;
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ncraddress : out std_logic_vector(5 downto 0);
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ncwrite : out std_ulogic;
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ncwdata : out std_logic_vector(8 downto 0);
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ncwaddress : out std_logic_vector(5 downto 0);
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ncrdata : in std_logic_vector(8 downto 0);
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--rmap buf
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rmrenable : out std_ulogic;
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rmraddress : out std_logic_vector(7 downto 0);
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rmwrite : out std_ulogic;
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rmwdata : out std_logic_vector(7 downto 0);
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rmwaddress : out std_logic_vector(7 downto 0);
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rmrdata : in std_logic_vector(7 downto 0);
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linkdis : out std_ulogic;
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testclk : in std_ulogic := '0';
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testrst : in std_ulogic := '0';
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testen : in std_ulogic := '0'
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);
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end component;
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component grspwc_unisim is
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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txclk : in std_ulogic;
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--ahb mst in
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hgrant : in std_ulogic;
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hready : in std_ulogic;
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hresp : in std_logic_vector(1 downto 0);
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hrdata : in std_logic_vector(31 downto 0);
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--ahb mst out
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hbusreq : out std_ulogic;
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hlock : out std_ulogic;
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htrans : out std_logic_vector(1 downto 0);
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haddr : out std_logic_vector(31 downto 0);
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hwrite : out std_ulogic;
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hsize : out std_logic_vector(2 downto 0);
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hburst : out std_logic_vector(2 downto 0);
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hprot : out std_logic_vector(3 downto 0);
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hwdata : out std_logic_vector(31 downto 0);
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--apb slv in
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psel : in std_ulogic;
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penable : in std_ulogic;
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paddr : in std_logic_vector(31 downto 0);
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pwrite : in std_ulogic;
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pwdata : in std_logic_vector(31 downto 0);
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--apb slv out
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prdata : out std_logic_vector(31 downto 0);
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--spw in
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di : in std_logic_vector(1 downto 0);
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si : in std_logic_vector(1 downto 0);
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--spw out
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do : out std_logic_vector(1 downto 0);
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so : out std_logic_vector(1 downto 0);
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--time iface
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tickin : in std_ulogic;
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tickout : out std_ulogic;
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--irq
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irq : out std_logic;
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--misc
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clkdiv10 : in std_logic_vector(7 downto 0);
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dcrstval : in std_logic_vector(9 downto 0);
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timerrstval : in std_logic_vector(11 downto 0);
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--rmapen
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rmapen : in std_ulogic;
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--clk bufs
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rxclki : in std_logic_vector(1 downto 0);
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nrxclki : in std_logic_vector(1 downto 0);
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rxclko : out std_logic_vector(1 downto 0);
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--rx ahb fifo
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rxrenable : out std_ulogic;
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rxraddress : out std_logic_vector(4 downto 0);
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rxwrite : out std_ulogic;
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rxwdata : out std_logic_vector(31 downto 0);
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rxwaddress : out std_logic_vector(4 downto 0);
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rxrdata : in std_logic_vector(31 downto 0);
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--tx ahb fifo
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txrenable : out std_ulogic;
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txraddress : out std_logic_vector(4 downto 0);
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txwrite : out std_ulogic;
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txwdata : out std_logic_vector(31 downto 0);
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txwaddress : out std_logic_vector(4 downto 0);
|
|
|
txrdata : in std_logic_vector(31 downto 0);
|
|
|
--nchar fifo
|
|
|
ncrenable : out std_ulogic;
|
|
|
ncraddress : out std_logic_vector(5 downto 0);
|
|
|
ncwrite : out std_ulogic;
|
|
|
ncwdata : out std_logic_vector(8 downto 0);
|
|
|
ncwaddress : out std_logic_vector(5 downto 0);
|
|
|
ncrdata : in std_logic_vector(8 downto 0);
|
|
|
--rmap buf
|
|
|
rmrenable : out std_ulogic;
|
|
|
rmraddress : out std_logic_vector(7 downto 0);
|
|
|
rmwrite : out std_ulogic;
|
|
|
rmwdata : out std_logic_vector(7 downto 0);
|
|
|
rmwaddress : out std_logic_vector(7 downto 0);
|
|
|
rmrdata : in std_logic_vector(7 downto 0);
|
|
|
linkdis : out std_ulogic;
|
|
|
testclk : in std_ulogic := '0';
|
|
|
testrst : in std_ulogic := '0';
|
|
|
testen : in std_ulogic := '0'
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component grspw_gen is
|
|
|
generic(
|
|
|
tech : integer := 0;
|
|
|
sysfreq : integer := 10000;
|
|
|
usegen : integer range 0 to 1 := 1;
|
|
|
nsync : integer range 1 to 2 := 1;
|
|
|
rmap : integer range 0 to 1 := 0;
|
|
|
rmapcrc : integer range 0 to 1 := 0;
|
|
|
fifosize1 : integer range 4 to 32 := 32;
|
|
|
fifosize2 : integer range 16 to 64 := 64;
|
|
|
rxclkbuftype : integer range 0 to 2 := 0;
|
|
|
rxunaligned : integer range 0 to 1 := 0;
|
|
|
rmapbufs : integer range 2 to 8 := 4;
|
|
|
ft : integer range 0 to 2 := 0;
|
|
|
scantest : integer range 0 to 1 := 0;
|
|
|
techfifo : integer range 0 to 1 := 1;
|
|
|
ports : integer range 1 to 2 := 1;
|
|
|
memtech : integer := 0;
|
|
|
nodeaddr : integer range 0 to 255 := 254;
|
|
|
destkey : integer range 0 to 255 := 0
|
|
|
);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
txclk : in std_ulogic;
|
|
|
--ahb mst in
|
|
|
hgrant : in std_ulogic;
|
|
|
hready : in std_ulogic;
|
|
|
hresp : in std_logic_vector(1 downto 0);
|
|
|
hrdata : in std_logic_vector(31 downto 0);
|
|
|
--ahb mst out
|
|
|
hbusreq : out std_ulogic;
|
|
|
hlock : out std_ulogic;
|
|
|
htrans : out std_logic_vector(1 downto 0);
|
|
|
haddr : out std_logic_vector(31 downto 0);
|
|
|
hwrite : out std_ulogic;
|
|
|
hsize : out std_logic_vector(2 downto 0);
|
|
|
hburst : out std_logic_vector(2 downto 0);
|
|
|
hprot : out std_logic_vector(3 downto 0);
|
|
|
hwdata : out std_logic_vector(31 downto 0);
|
|
|
--apb slv in
|
|
|
psel : in std_ulogic;
|
|
|
penable : in std_ulogic;
|
|
|
paddr : in std_logic_vector(31 downto 0);
|
|
|
pwrite : in std_ulogic;
|
|
|
pwdata : in std_logic_vector(31 downto 0);
|
|
|
--apb slv out
|
|
|
prdata : out std_logic_vector(31 downto 0);
|
|
|
--spw in
|
|
|
di : in std_logic_vector(1 downto 0);
|
|
|
si : in std_logic_vector(1 downto 0);
|
|
|
--spw out
|
|
|
do : out std_logic_vector(1 downto 0);
|
|
|
so : out std_logic_vector(1 downto 0);
|
|
|
--time iface
|
|
|
tickin : in std_ulogic;
|
|
|
tickout : out std_ulogic;
|
|
|
--irq
|
|
|
irq : out std_logic;
|
|
|
--misc
|
|
|
clkdiv10 : in std_logic_vector(7 downto 0);
|
|
|
dcrstval : in std_logic_vector(9 downto 0);
|
|
|
timerrstval : in std_logic_vector(11 downto 0);
|
|
|
--rmapen
|
|
|
rmapen : in std_ulogic;
|
|
|
linkdis : out std_ulogic;
|
|
|
testclk : in std_ulogic := '0';
|
|
|
testrst : in std_ulogic := '0';
|
|
|
testen : in std_ulogic := '0'
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component grspw_codec_core is
|
|
|
generic(
|
|
|
ports : integer range 1 to 2 := 1;
|
|
|
input_type : integer range 0 to 3 := 0;
|
|
|
output_type : integer range 0 to 2 := 0;
|
|
|
rxtx_sameclk : integer range 0 to 1 := 0;
|
|
|
fifosize : integer range 16 to 2048 := 64;
|
|
|
tech : integer;
|
|
|
scantest : integer range 0 to 1 := 0
|
|
|
);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
rxclk0 : in std_ulogic;
|
|
|
rxclk1 : in std_ulogic;
|
|
|
txclk : in std_ulogic;
|
|
|
txclkn : in std_ulogic;
|
|
|
testen : in std_ulogic;
|
|
|
testrst : in std_ulogic;
|
|
|
--spw in
|
|
|
d : in std_logic_vector(3 downto 0);
|
|
|
dv : in std_logic_vector(3 downto 0);
|
|
|
dconnect : in std_logic_vector(3 downto 0);
|
|
|
--spw out
|
|
|
do : out std_logic_vector(3 downto 0);
|
|
|
so : out std_logic_vector(3 downto 0);
|
|
|
--link fsm
|
|
|
linkdisabled : in std_ulogic;
|
|
|
linkstart : in std_ulogic;
|
|
|
autostart : in std_ulogic;
|
|
|
portsel : in std_ulogic;
|
|
|
noportforce : in std_ulogic;
|
|
|
rdivisor : in std_logic_vector(7 downto 0);
|
|
|
idivisor : in std_logic_vector(7 downto 0);
|
|
|
state : out std_logic_vector(2 downto 0);
|
|
|
actport : out std_ulogic;
|
|
|
dconnecterr : out std_ulogic;
|
|
|
crederr : out std_ulogic;
|
|
|
escerr : out std_ulogic;
|
|
|
parerr : out std_ulogic;
|
|
|
--rx fifo signals
|
|
|
rxrenable : out std_ulogic;
|
|
|
rxraddress : out std_logic_vector(10 downto 0);
|
|
|
rxwrite : out std_ulogic;
|
|
|
rxwdata : out std_logic_vector(9 downto 0);
|
|
|
rxwaddress : out std_logic_vector(10 downto 0);
|
|
|
rxrdata : in std_logic_vector(9 downto 0);
|
|
|
rxaccess : out std_ulogic;
|
|
|
--rx iface
|
|
|
rxicharav : out std_ulogic;
|
|
|
rxicharcnt : out std_logic_vector(11 downto 0);
|
|
|
rxichar : out std_logic_vector(8 downto 0);
|
|
|
rxiread : in std_ulogic;
|
|
|
rxififorst : in std_ulogic;
|
|
|
--tx fifo signals
|
|
|
txrenable : out std_ulogic;
|
|
|
txraddress : out std_logic_vector(10 downto 0);
|
|
|
txwrite : out std_ulogic;
|
|
|
txwdata : out std_logic_vector(8 downto 0);
|
|
|
txwaddress : out std_logic_vector(10 downto 0);
|
|
|
txrdata : in std_logic_vector(8 downto 0);
|
|
|
txaccess : out std_ulogic;
|
|
|
--tx iface
|
|
|
txicharcnt : out std_logic_vector(11 downto 0);
|
|
|
txifull : out std_ulogic;
|
|
|
txiempty : out std_ulogic;
|
|
|
txiwrite : in std_ulogic;
|
|
|
txichar : in std_logic_vector(8 downto 0);
|
|
|
txififorst : in std_ulogic;
|
|
|
txififorstact: out std_ulogic;
|
|
|
--time iface
|
|
|
tickin : in std_ulogic;
|
|
|
timein : in std_logic_vector(7 downto 0);
|
|
|
tickin_done : out std_ulogic;
|
|
|
tickout : out std_ulogic;
|
|
|
timeout : out std_logic_vector(7 downto 0)
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
component grspw2_gen is
|
|
|
generic(
|
|
|
rmap : integer range 0 to 1 := 0;
|
|
|
rmapcrc : integer range 0 to 1 := 0;
|
|
|
fifosize1 : integer range 4 to 32 := 32;
|
|
|
fifosize2 : integer range 16 to 64 := 64;
|
|
|
rxunaligned : integer range 0 to 1 := 0;
|
|
|
rmapbufs : integer range 2 to 8 := 4;
|
|
|
scantest : integer range 0 to 1 := 0;
|
|
|
ports : integer range 1 to 2 := 1;
|
|
|
dmachan : integer range 1 to 4 := 1;
|
|
|
tech : integer;
|
|
|
input_type : integer range 0 to 3 := 0;
|
|
|
output_type : integer range 0 to 2 := 0;
|
|
|
rxtx_sameclk : integer range 0 to 1 := 0;
|
|
|
ft : integer range 0 to 2 := 0;
|
|
|
techfifo : integer range 0 to 1 := 1;
|
|
|
memtech : integer := 0);
|
|
|
port(
|
|
|
rst : in std_ulogic;
|
|
|
clk : in std_ulogic;
|
|
|
rxclk0 : in std_ulogic;
|
|
|
rxclk1 : in std_ulogic;
|
|
|
txclk : in std_ulogic;
|
|
|
txclkn : in std_ulogic;
|
|
|
--ahb mst in
|
|
|
hgrant : in std_ulogic;
|
|
|
hready : in std_ulogic;
|
|
|
hresp : in std_logic_vector(1 downto 0);
|
|
|
hrdata : in std_logic_vector(31 downto 0);
|
|
|
--ahb mst out
|
|
|
hbusreq : out std_ulogic;
|
|
|
hlock : out std_ulogic;
|
|
|
htrans : out std_logic_vector(1 downto 0);
|
|
|
haddr : out std_logic_vector(31 downto 0);
|
|
|
hwrite : out std_ulogic;
|
|
|
hsize : out std_logic_vector(2 downto 0);
|
|
|
hburst : out std_logic_vector(2 downto 0);
|
|
|
hprot : out std_logic_vector(3 downto 0);
|
|
|
hwdata : out std_logic_vector(31 downto 0);
|
|
|
--apb slv in
|
|
|
psel : in std_ulogic;
|
|
|
penable : in std_ulogic;
|
|
|
paddr : in std_logic_vector(31 downto 0);
|
|
|
pwrite : in std_ulogic;
|
|
|
pwdata : in std_logic_vector(31 downto 0);
|
|
|
--apb slv out
|
|
|
prdata : out std_logic_vector(31 downto 0);
|
|
|
--spw in
|
|
|
d : in std_logic_vector(3 downto 0);
|
|
|
dv : in std_logic_vector(3 downto 0);
|
|
|
dconnect : in std_logic_vector(3 downto 0);
|
|
|
--spw out
|
|
|
do : out std_logic_vector(3 downto 0);
|
|
|
so : out std_logic_vector(3 downto 0);
|
|
|
--time iface
|
|
|
tickin : in std_ulogic;
|
|
|
tickinraw : in std_ulogic;
|
|
|
timein : in std_logic_vector(7 downto 0);
|
|
|
tickindone : out std_ulogic;
|
|
|
tickout : out std_ulogic;
|
|
|
tickoutraw : out std_ulogic;
|
|
|
timeout : out std_logic_vector(7 downto 0);
|
|
|
--irq
|
|
|
irq : out std_logic;
|
|
|
--misc
|
|
|
clkdiv10 : in std_logic_vector(7 downto 0);
|
|
|
linkdis : out std_ulogic;
|
|
|
testrst : in std_ulogic := '0';
|
|
|
testen : in std_ulogic := '0';
|
|
|
--rmapen
|
|
|
rmapen : in std_ulogic;
|
|
|
--parallel rx data out
|
|
|
rxdav : out std_ulogic;
|
|
|
rxdataout : out std_logic_vector(8 downto 0)
|
|
|
);
|
|
|
end component;
|
|
|
|
|
|
end package;
|
|
|
|
