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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.iir_filter.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.general_purpose.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY RAM_CTRLR_v2 IS
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GENERIC(
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tech : INTEGER := 0;
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Input_SZ_1 : INTEGER := 16;
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Mem_use : INTEGER := use_RAM
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);
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PORT(
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rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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-- R/W Ctrl
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ram_write : IN STD_LOGIC;
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ram_read : IN STD_LOGIC;
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-- ADDR Ctrl
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raddr_rst : IN STD_LOGIC;
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raddr_add1 : IN STD_LOGIC;
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waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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-- Data
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sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
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sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
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);
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END RAM_CTRLR_v2;
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ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
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SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
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SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
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SIGNAL WEN, REN : STD_LOGIC;
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SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
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BEGIN
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sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
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WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
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-----------------------------------------------------------------------------
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-- RAM
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-----------------------------------------------------------------------------
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memCEL : IF Mem_use = use_CEL GENERATE
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WEN <= NOT ram_write;
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REN <= NOT ram_read;
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-- RAMblk : RAM_CEL_N
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RAMblk : RAM_CEL_N
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GENERIC MAP(Input_SZ_1)
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PORT MAP(
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WD => WD,
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RD => RD,
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WEN => WEN,
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REN => REN,
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WADDR => WADDR,
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RADDR => RADDR,
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RWCLK => clk,
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RESET => rstn
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) ;
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END GENERATE;
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memRAM : IF Mem_use = use_RAM GENERATE
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SRAM : syncram_2p
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GENERIC MAP(tech, 8, Input_SZ_1)
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PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
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END GENERATE;
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-----------------------------------------------------------------------------
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-- RADDR
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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counter <= (OTHERS => '0');
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF raddr_rst = '1' THEN
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counter <= (OTHERS => '0');
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ELSIF raddr_add1 = '1' THEN
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counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
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END IF;
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END IF;
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END PROCESS;
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RADDR <= counter;
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-----------------------------------------------------------------------------
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-- WADDR
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-----------------------------------------------------------------------------
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WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
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STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
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STD_LOGIC_VECTOR(UNSIGNED(counter));
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END ar_RAM_CTRLR_v2;
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