HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-M7A3P1k/synthesis/leon3mp.pdc

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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib

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DAC CAL input data via Registre_data Driver C

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/ designs / ProjetBlanc-LeonLPP-M7A3P1k / synthesis / leon3mp.pdc

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				# Actel Physical design constraints file
				# Version: 7.2 7.2.0.103
				# Input Netlist Format: edif


				#
				# I/O Constraints
				#

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