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-- TOP_Serial_Driver_Wcounter.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity TOP_Serial_Driver_Wcounter is
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Generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64);
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port(
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clk : in std_logic;
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sclk : in std_logic;
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Gate : in std_logic;
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MinF : in std_logic;
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MajF : in std_logic;
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Data : out std_logic
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);
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end entity;
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architecture ar_TOP_Serial_Driver_Wcounter of TOP_Serial_Driver_Wcounter is
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Constant FramePlacerCount : integer := 2;
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signal MinF_Inv : std_logic;
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signal Gate_Inv : std_logic;
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signal sclk_Inv : std_logic;
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signal WordCount : integer range 0 to WordCnt-1;
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signal WordClk : std_logic;
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signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
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signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
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signal Sel : integer range 0 to 1;
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signal DC1 : std_logic_vector(23 downto 0);
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signal DC2 : std_logic_vector(23 downto 0);
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signal DC3 : std_logic_vector(23 downto 0);
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signal LF1 : std_logic_vector(15 downto 0);
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signal LF2 : std_logic_vector(15 downto 0);
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signal LF3 : std_logic_vector(15 downto 0);
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constant DC1cst : std_logic_vector(23 downto 0) := X"FA5961";
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constant DC2cst : std_logic_vector(23 downto 0) := X"123456";
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constant DC3cst : std_logic_vector(23 downto 0) := X"789012";
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constant LF1cst : std_logic_vector(15 downto 0) := X"3210";
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constant LF2cst : std_logic_vector(15 downto 0) := X"6543";
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constant LF3cst : std_logic_vector(15 downto 0) := X"3456";
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signal MinFCnt : integer range 0 to MinFCount-1;
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signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
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begin
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Gate_Inv <= not Gate;
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sclk_Inv <= not Sclk;
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MinF_Inv <= not MinF;
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DC1 <= DC1cst;
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DC2 <= DC2cst;
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DC3 <= DC3cst;
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LF1 <= LF1cst;
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LF2 <= LF2cst;
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LF3 <= LF3cst;
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SD0 : entity work.Serial_Driver
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generic map(WordSize)
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port map(sclk_Inv,MuxOUT,Gate_inv,Data);
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WC0 : entity work.Word_Cntr
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generic map(WordSize,WordCnt)
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port map(sclk_Inv,MinF,WordClk,WordCount);
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MFC0 : entity work.MinF_Cntr
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generic map(MinFCount)
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port map(
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clk => MinF_Inv,
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reset => MajF,
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Cnt_out => MinFCnt
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);
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MUX0 : entity work.Serial_Driver_Multiplexor
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generic map(FramePlacerCount,WordSize)
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port map(sclk_Inv,Sel,MuxIN,MuxOUT);
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DCFP0 : entity work.DC_FRAME_PLACER
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generic map(WordSize,WordCnt,MinFCount)
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port map(
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clk => Sclk,
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Wcount => WordCount,
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MinFCnt => MinFCnt,
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Flag => FramePlacerFlags(0),
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DC1 => DC1,
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DC2 => DC2,
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DC3 => DC3,
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WordOut => MuxIN(7 downto 0));
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LFP0 : entity work.LF_FRAME_PLACER
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generic map(WordSize,WordCnt,MinFCount)
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port map(
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clk => Sclk,
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Wcount => WordCount,
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Flag => FramePlacerFlags(1),
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LF1 => LF1,
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LF2 => LF2,
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LF3 => LF3,
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WordOut => MuxIN(15 downto 8));
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-- FramePlacerFlags(1) <= '0';
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-- MuxIN(15 downto 8) <= (others =>'0');
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--Input Word Selection Decoder
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process(clk)
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variable SelVar : integer range 0 to 1;
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begin
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if clk'event and clk ='1' then
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Decoder: FOR i IN 0 to FramePlacerCount-1 loop
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if FramePlacerFlags(i) = '1' then
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SelVar := i;
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end if;
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END loop Decoder;
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Sel <= SelVar;
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end if;
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end process;
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end ar_TOP_Serial_Driver_Wcounter;
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