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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_waveform_fifo_latencyCorrection IS
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GENERIC(
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tech : INTEGER := 0
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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run : IN STD_LOGIC;
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---------------------------------------------------------------------------
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empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b
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empty : OUT STD_LOGIC;
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data_ren : IN STD_LOGIC;
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rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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---------------------------------------------------------------------------
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empty_almost_fifo : IN STD_LOGIC;
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empty_fifo : IN STD_LOGIC;
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data_ren_fifo : OUT STD_LOGIC;
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rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_waveform_fifo_latencyCorrection OF lpp_waveform_fifo_latencyCorrection IS
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SIGNAL data_ren_fifo_s : STD_LOGIC;
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-- SIGNAL rdata_s : STD_LOGIC;
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SIGNAL reg_full : STD_LOGIC;
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SIGNAL empty_almost_reg : STD_LOGIC;
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BEGIN
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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empty_almost_reg <= '1';
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empty <= '1';
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data_ren_fifo_s <= '1';
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rdata <= (OTHERS => '0');
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reg_full <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF run = '0' THEN
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empty_almost_reg <= '1';
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empty <= '1';
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data_ren_fifo_s <= '1';
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rdata <= (OTHERS => '0');
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reg_full <= '0';
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ELSE
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IF data_ren_fifo_s = '0' THEN
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reg_full <= '1';
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ELSIF data_ren = '0' THEN
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reg_full <= '0';
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END IF;
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IF data_ren_fifo_s = '0' THEN
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rdata <= rdata_fifo;
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END IF;
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IF (reg_full = '0' OR data_ren = '0') AND empty_fifo = '0' THEN
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data_ren_fifo_s <= '0';
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ELSE
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data_ren_fifo_s <= '1';
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END IF;
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IF empty_fifo = '1' AND ((reg_full = '0') OR ( data_ren = '0')) THEN
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empty <= '1';
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ELSE
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empty <= '0';
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END IF;
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IF empty_almost_reg = '0' AND data_ren = '0' AND empty_almost_fifo = '1' THEN
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empty_almost_reg <= '1';
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ELSIF empty_almost_reg = '1' AND empty_almost_fifo = '0' THEN
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empty_almost_reg <= '0';
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END IF;
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END IF;
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END IF;
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END PROCESS;
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empty_almost <= empty_almost_reg;
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data_ren_fifo <= data_ren_fifo_s;
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END ARCHITECTURE;
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