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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Jean-christophe PELLION
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.lpp_waveform_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_waveform_fifo_headreg IS
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GENERIC(
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tech : INTEGER := 0
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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---------------------------------------------------------------------------
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run : IN STD_LOGIC;
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---------------------------------------------------------------------------
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o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
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o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
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---------------------------------------------------------------------------
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i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
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i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS
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SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL one_ren_and_notEmpty : STD_LOGIC;
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SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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-- DATA_REN_FIFO
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-----------------------------------------------------------------------------
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i_data_ren <= s_ren;
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PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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s_ren_reg <= (OTHERS => '1');
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ELSIF clk'EVENT AND clk = '1' THEN
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IF run = '1' THEN
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s_ren_reg <= s_ren;
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ELSE
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s_ren_reg <= (OTHERS => '1');
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END IF;
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END IF;
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END PROCESS;
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s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE
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NOT ((NOT i_empty(0)) AND (NOT reg_full(0)));
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s_ren(1) <= '1' WHEN s_ren(0) = '0' ELSE
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o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
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NOT ((NOT i_empty(1)) AND (NOT reg_full(1)));
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s_ren(2) <= '1' WHEN s_ren(0) = '0' ELSE
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'1' WHEN s_ren(1) = '0' ELSE
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o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
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NOT ((NOT i_empty(2)) AND (NOT reg_full(2)));
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s_ren(3) <= '1' WHEN s_ren(0) = '0' ELSE
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'1' WHEN s_ren(1) = '0' ELSE
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'1' WHEN s_ren(2) = '0' ELSE
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o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
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NOT ((NOT i_empty(3)) AND (NOT reg_full(3)));
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-----------------------------------------------------------------------------
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all_ren : FOR I IN 3 DOWNTO 0 GENERATE
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ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I));
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END GENERATE all_ren;
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one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1';
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-----------------------------------------------------------------------------
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-- DATA
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-----------------------------------------------------------------------------
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o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0;
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o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1;
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o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2;
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o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3;
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PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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s_rdata_0 <= (OTHERS => '0');
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s_rdata_1 <= (OTHERS => '0');
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s_rdata_2 <= (OTHERS => '0');
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s_rdata_3 <= (OTHERS => '0');
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ELSIF clk'EVENT AND clk = '1' THEN
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IF run = '1' THEN
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IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
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IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
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IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
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IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
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ELSE
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s_rdata_0 <= (OTHERS => '0');
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s_rdata_1 <= (OTHERS => '0');
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s_rdata_2 <= (OTHERS => '0');
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s_rdata_3 <= (OTHERS => '0');
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END IF;
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END IF;
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END PROCESS;
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all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE
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PROCESS (clk, rstn)
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BEGIN
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IF rstn = '0' THEN
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reg_full(I) <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN
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-- IF s_ren_reg(I) = '0' THEN
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IF run = '1' THEN
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IF s_ren(I) = '0' THEN
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reg_full(I) <= '1';
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ELSIF o_data_ren(I) = '0' THEN
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reg_full(I) <= '0';
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END IF;
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ELSE
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reg_full(I) <= '0';
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END IF;
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END IF;
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END PROCESS;
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END GENERATE all_reg_full;
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-----------------------------------------------------------------------------
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-- EMPTY
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-----------------------------------------------------------------------------
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o_empty <= NOT reg_full;
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-----------------------------------------------------------------------------
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-- EMPTY_ALMOST
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-----------------------------------------------------------------------------
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o_empty_almost <= s_empty_almost;
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all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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s_empty_almost(I) <= '1';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF run = '1' THEN
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IF s_ren(I) = '0' THEN
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s_empty_almost(I) <= i_empty_almost(I);
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ELSIF o_data_ren(I) = '0' THEN
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s_empty_almost(I) <= '1';
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ELSE
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IF i_empty_almost(I) = '0' THEN
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s_empty_almost(I) <= '0';
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END IF;
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END IF;
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ELSE
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s_empty_almost(I) <= '1';
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END IF;
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END IF;
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END PROCESS;
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END GENERATE all_empty_almost;
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END ARCHITECTURE;
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