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------------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.net.all;
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use gaisler.jtag.all;
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library esa;
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use esa.memoryctrl.all;
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use work.config.all;
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library lpp;
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use lpp.amba_lcd_16x2_ctrlr.all;
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use lpp.LCD_16x2_CFG.all;
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use lpp.lpp_ad_conv.all;
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use lpp.iir_filter.all;
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use lpp.general_purpose.all;
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use lpp.lpp_uart.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
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);
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port (
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reset : in std_ulogic;
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-- resoutn : out std_logic;
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clk_50mhz : in std_ulogic;
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errorn : out std_ulogic;
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-- prom interface
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address : out std_logic_vector(23 downto 0);
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data : inout std_logic_vector(15 downto 0);
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romsn : out std_ulogic;
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oen : out std_ulogic;
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writen : out std_ulogic;
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byten : out std_ulogic;
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-- pragma translate_off
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iosn : out std_ulogic;
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testdata : inout std_logic_vector(15 downto 0);
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-- pragma translate_on
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-- ddr memory
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ddr_clk0 : out std_logic;
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ddr_clk0b : out std_logic;
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-- ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke0 : out std_logic;
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ddr_cs0b : out std_logic;
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
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-- debug support unit
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dsuen : in std_ulogic;
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dsubre : in std_ulogic;
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-- dsuact : out std_ulogic;
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dsurx : in std_ulogic;
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dsutx : out std_ulogic;
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-- UART for serial console I/O
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urxd1 : in std_ulogic;
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utxd1 : out std_ulogic;
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-- ethernet signals
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emdio : inout std_logic; -- ethernet PHY interface
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etx_clk : in std_ulogic;
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erx_clk : in std_ulogic;
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erxd : in std_logic_vector(3 downto 0);
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erx_dv : in std_ulogic;
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erx_er : in std_ulogic;
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erx_col : in std_ulogic;
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erx_crs : in std_ulogic;
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etxd : out std_logic_vector(3 downto 0);
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etx_en : out std_ulogic;
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etx_er : out std_ulogic;
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emdc : out std_ulogic;
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spi : out std_ulogic;
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led : out std_logic_vector(5 downto 0);
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ps2clk : inout std_logic;
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ps2data : inout std_logic;
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vid_hsync : out std_ulogic;
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vid_vsync : out std_ulogic;
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vid_r : out std_logic;
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vid_g : out std_logic;
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vid_b : out std_logic;
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LCD_RS : out STD_LOGIC;
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LCD_RW : out STD_LOGIC;
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LCD_E : out STD_LOGIC;
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LCD_RET : out STD_LOGIC;
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LCD_CS1 : out STD_LOGIC;
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LCD_CS2 : out STD_LOGIC;
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SF_CE0 : out std_logic;
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BTN_NORTH : in std_ulogic;
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BTN_WEST : in std_ulogic;
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ADC_SCK : out std_logic;
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ADC_CNV : out std_logic;
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ADC_SDI : in std_logic;
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lppTXD : out std_logic;
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lppRXD : in std_logic
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);
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end;
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architecture rtl of leon3mp is
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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signal vcc, gnd : std_logic_vector(4 downto 0);
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdi : sdctrl_in_type;
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signal sdo : sdctrl_out_type;
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal lclk : std_ulogic;
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signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
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signal clkm, rstn, clkml, clk2x : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal u1i, dui : uart_in_type;
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signal u1o, duo : uart_out_type;
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal ethi, ethi1, ethi2 : eth_in_type;
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signal etho, etho1, etho2 : eth_out_type;
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signal gpti : gptimer_in_type;
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signal tck, tms, tdi, tdo : std_ulogic;
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signal kbdi : ps2_in_type;
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signal kbdo : ps2_out_type;
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signal vgao : apbvga_out_type;
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signal ldsubre : std_logic;
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signal duart, ldsuen : std_logic;
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signal rsertx, rserrx, rdsuen : std_logic;
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signal rstraw : std_logic;
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signal rstneg : std_logic;
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signal rxd1, rxd2 : std_logic;
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signal txd1 : std_logic;
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signal lock : std_logic;
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signal ddr_clk : std_logic_vector(2 downto 0);
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signal ddr_clkb : std_logic_vector(2 downto 0);
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signal ddr_cke : std_logic_vector(1 downto 0);
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signal ddr_csb : std_logic_vector(1 downto 0);
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signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
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signal AD_in : AD7688_in(0 downto 0);
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signal AD_out : AD7688_out;
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signal smpclk_out : std_logic;
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signal smpclk_in : std_logic;
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signal sample_out : samplT(0 downto 0,11 downto 0);
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signal sample_in : samplT(0 downto 0,11 downto 0);
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signal sample_clk : std_logic;
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signal sample_clk_out : std_logic;
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attribute keep : boolean;
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attribute syn_keep : boolean;
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attribute syn_preserve : boolean;
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attribute syn_keep of lock : signal is true;
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attribute syn_keep of clkml : signal is true;
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attribute syn_preserve of clkml : signal is true;
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attribute keep of lock : signal is true;
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attribute keep of clkml : signal is true;
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attribute keep of clkm : signal is true;
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constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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begin
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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rstneg <= not reset; spi <= '1';
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rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
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led(5) <= lock;
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clk_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk);
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clkgen0 : clkgen -- clock generator
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generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
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port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
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-- cgo.clklock <= '1';
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
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nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
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nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- LEON3 processor and DSU -----------------------------------------
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----------------------------------------------------------------------
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leon3gen : if CFG_LEON3 = 1 generate
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cpu : for i in 0 to CFG_NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
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CFG_NCPU-1)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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end generate;
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error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
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dsugen : if CFG_DSU = 1 generate
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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dsui.enable <= '1';
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dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
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dsui.break <= ldsubre;
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-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
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led(4) <= dsuo.active;
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end generate;
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end generate;
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nodsu : if CFG_DSU = 0 generate
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ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
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end generate;
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dcomgen : if CFG_AHB_UART = 1 generate
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dcom0 : ahbuart -- Debug UART
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generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
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port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
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dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd2);
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dui.rxd <= rxd2;
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dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
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led(2) <= not rxd2; led(3) <= not duo.txd;
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end generate;
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nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
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ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
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ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
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port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
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open, open, open, open, open, open, open, gnd(0));
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end generate;
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----------------------------------------------------------------------
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--- Memory controllers ----------------------------------------------
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----------------------------------------------------------------------
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mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
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sr1 : mctrl generic map (hindex => 5, pindex => 0,
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paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
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port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
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end generate;
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byten <= '1'; -- 16-bit flash
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memi.brdyn <= '1'; memi.bexcn <= '1';
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memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
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mg0 : if (CFG_MCTRL_LEON2 = 0) generate
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apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
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roms_pad : outpad generic map (tech => padtech)
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port map (romsn, vcc(0));
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end generate;
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mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
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addr_pad : outpadv generic map (width => 24, tech => padtech)
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port map (address, memo.address(23 downto 0));
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roms_pad : outpad generic map (tech => padtech)
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port map (romsn, memo.romsn(0));
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oen_pad : outpad generic map (tech => padtech)
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port map (oen, memo.oen);
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wri_pad : outpad generic map (tech => padtech)
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port map (writen, memo.writen);
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-- pragma translate_off
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iosn_pad : outpad generic map (tech => padtech)
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port map (iosn, memo.iosn);
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tbdr : for i in 0 to 1 generate
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data_pad : iopadv generic map (tech => padtech, width => 8)
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port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
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memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
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end generate;
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-- pragma translate_on
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-- bdr : for i in 0 to 1 generate
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-- data_pad : iopadv generic map (tech => padtech, width => 8)
|
|
|
-- port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
|
|
|
-- memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
|
|
|
-- end generate;
|
|
|
end generate;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- DDR memory controller -------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
ddrsp0 : if (CFG_DDRSP /= 0) generate
|
|
|
|
|
|
ddrc : ddrspa generic map ( fabtech => spartan3e, memtech => memtech,
|
|
|
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
|
|
|
pwron => CFG_DDRSP_INIT, MHz => 2*BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
|
|
|
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 2*5, col => CFG_DDRSP_COL,
|
|
|
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
|
|
|
port map (
|
|
|
cgo.clklock, rstn, clk2x, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
|
|
|
ddr_clk, ddr_clkb, open, ddr_clk_fb,
|
|
|
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
|
|
|
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
|
|
|
|
|
|
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
|
|
|
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
|
|
|
ddr_ad <= ddr_adl(12 downto 0);
|
|
|
end generate;
|
|
|
|
|
|
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- APB Bridge and various periherals -------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
apb0 : apbctrl -- AHB/APB bridge
|
|
|
generic map (hindex => 1, haddr => CFG_APBADDR)
|
|
|
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
|
|
|
|
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
|
|
uart1 : apbuart -- UART 1
|
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
|
|
fifosize => CFG_UART1_FIFO)
|
|
|
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
|
|
|
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
|
|
|
serrx_pad : inpad generic map (tech => padtech) port map (urxd1, rxd1);
|
|
|
sertx_pad : outpad generic map (tech => padtech) port map (utxd1, txd1);
|
|
|
led(0) <= not rxd1; led(1) <= not txd1;
|
|
|
end generate;
|
|
|
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
|
|
|
|
|
|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
|
|
|
irqctrl0 : irqmp -- interrupt controller
|
|
|
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
|
|
|
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
|
|
|
end generate;
|
|
|
irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
|
|
x : for i in 0 to CFG_NCPU-1 generate
|
|
|
irqi(i).irl <= "0000";
|
|
|
end generate;
|
|
|
apbo(2) <= apb_none;
|
|
|
end generate;
|
|
|
|
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
|
|
timer0 : gptimer -- timer unit
|
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
|
|
nbits => CFG_GPT_TW)
|
|
|
port map (rstn, clkm, apbi, apbo(3), gpti, open);
|
|
|
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
|
|
|
end generate;
|
|
|
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
|
|
|
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
|
|
|
grgpio0: grgpio
|
|
|
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
|
|
|
nbits => 12 --CFG_GRGPIO_WIDTH
|
|
|
)
|
|
|
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
|
|
|
|
|
|
end generate;
|
|
|
|
|
|
kbd : if CFG_KBD_ENABLE /= 0 generate
|
|
|
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
|
|
|
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
|
|
|
kbdclk_pad : iopad generic map (tech => padtech)
|
|
|
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
|
|
|
kbdata_pad : iopad generic map (tech => padtech)
|
|
|
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
|
|
|
end generate;
|
|
|
nokbd : if CFG_KBD_ENABLE = 0 generate
|
|
|
apbo(5) <= apb_none; kbdo <= ps2o_none;
|
|
|
end generate;
|
|
|
|
|
|
-- vga : if CFG_VGA_ENABLE /= 0 generate
|
|
|
-- vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
|
|
|
-- port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
|
|
|
-- video_clock_pad : outpad generic map ( tech => padtech)
|
|
|
-- port map (vid_clock, dac_clk);
|
|
|
-- dac_clk <= not clkm;
|
|
|
-- end generate;
|
|
|
|
|
|
svga : if CFG_SVGA_ENABLE /= 0 generate
|
|
|
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
|
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
|
|
|
clk0 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
|
|
|
clk1 => 0, clk2 => 0, burstlen => 5)
|
|
|
port map(rstn, clkm, clkm, apbi, apbo(6), vgao, ahbmi,
|
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
|
|
|
end generate;
|
|
|
|
|
|
-- blank_pad : outpad generic map (tech => padtech)
|
|
|
-- port map (vid_blankn, vgao.blank);
|
|
|
-- comp_sync_pad : outpad generic map (tech => padtech)
|
|
|
-- port map (vid_syncn, vgao.comp_sync);
|
|
|
vert_sync_pad : outpad generic map (tech => padtech)
|
|
|
port map (vid_vsync, vgao.vsync);
|
|
|
horiz_sync_pad : outpad generic map (tech => padtech)
|
|
|
port map (vid_hsync, vgao.hsync);
|
|
|
video_out_r_pad : outpad generic map (tech => padtech)
|
|
|
port map (vid_r, vgao.video_out_r(7));
|
|
|
video_out_g_pad : outpad generic map (tech => padtech)
|
|
|
port map (vid_g, vgao.video_out_g(7));
|
|
|
video_out_b_pad : outpad generic map (tech => padtech)
|
|
|
port map (vid_b, vgao.video_out_b(7));
|
|
|
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- LCD CONTROLER ----------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
LCD0 : apb_lcd_ctrlr
|
|
|
generic map( 8, 8,16#fff#,0,8)
|
|
|
Port map( rstn,clkm,apbi, apbo(8),data(15 downto 8),LCD_RS,LCD_RW,LCD_E,LCD_RET,LCD_CS1,LCD_CS2,SF_CE0);
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
-------- LPP UART ----------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
LPPUART0: APB_UART
|
|
|
generic map( 12, 12,16#fff#,0,8,8)
|
|
|
port map(clkm,rstn,apbi, apbo(12),lppTXD,lppRXD);
|
|
|
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- ADS7886 ----------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
ADC0 : lpp_apb_ad_conv
|
|
|
generic map(9,9,16#fff#,0,8,1,50000,100,ADS7886)
|
|
|
Port map(clkm,rstn,apbi, apbo(9),AD_in,AD_out);
|
|
|
|
|
|
AD_in(0).SDI <= ADC_SDI;
|
|
|
ADC_CNV <= AD_out.CNV;
|
|
|
ADC_SCK <= AD_out.SCK;
|
|
|
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- I I R F I L T E R --------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
smplclkgen: Clk_divider
|
|
|
generic map(40000000,1000)
|
|
|
Port map( clkm ,rstn,sample_clk);
|
|
|
|
|
|
|
|
|
FILTER0: APB_IIR_CEL
|
|
|
generic map(10,10,16#fff#,0,8,1,12,9,3,5,use_RAM)
|
|
|
port map(rstn,clkm,apbi, apbo(10),sample_clk,sample_clk_out,sample_in,sample_out
|
|
|
);
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- ETHERNET ---------------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
|
|
|
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
|
|
|
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
|
|
|
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
|
|
|
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
|
|
|
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
|
|
|
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
|
|
|
phyrstadr => 31, giga => CFG_GRETH1G)
|
|
|
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
|
|
|
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
|
|
|
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
|
|
|
|
|
|
emdio_pad : iopad generic map (tech => padtech)
|
|
|
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
|
|
|
etxc_pad : inpad generic map (tech => padtech)
|
|
|
port map (etx_clk, ethi.tx_clk);
|
|
|
erxc_pad : inpad generic map (tech => padtech)
|
|
|
port map (erx_clk, ethi.rx_clk);
|
|
|
erxd_pad : inpadv generic map (tech => padtech, width => 4)
|
|
|
port map (erxd, ethi.rxd(3 downto 0));
|
|
|
erxdv_pad : inpad generic map (tech => padtech)
|
|
|
port map (erx_dv, ethi.rx_dv);
|
|
|
erxer_pad : inpad generic map (tech => padtech)
|
|
|
port map (erx_er, ethi.rx_er);
|
|
|
erxco_pad : inpad generic map (tech => padtech)
|
|
|
port map (erx_col, ethi.rx_col);
|
|
|
erxcr_pad : inpad generic map (tech => padtech)
|
|
|
port map (erx_crs, ethi.rx_crs);
|
|
|
|
|
|
etxd_pad : outpadv generic map (tech => padtech, width => 4)
|
|
|
port map (etxd, etho.txd(3 downto 0));
|
|
|
etxen_pad : outpad generic map (tech => padtech)
|
|
|
port map (etx_en, etho.tx_en);
|
|
|
etxer_pad : outpad generic map (tech => padtech)
|
|
|
port map (etx_er, etho.tx_er);
|
|
|
emdc_pad : outpad generic map (tech => padtech)
|
|
|
port map (emdc, etho.mdc);
|
|
|
|
|
|
end generate;
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- AHB DMA ----------------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
-- dma0 : ahbdma
|
|
|
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
|
|
|
-- pindex => 12, paddr => 12, dbuf => 32)
|
|
|
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
|
|
|
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
|
|
|
--
|
|
|
-- at0 : ahbtrace
|
|
|
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
|
|
|
-- tech => memtech, irq => 0, kbytes => 8)
|
|
|
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- AHB ROM ----------------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
bpromgen : if CFG_AHBROMEN /= 0 generate
|
|
|
brom : entity work.ahbrom
|
|
|
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
|
|
|
port map ( rstn, clkm, ahbsi, ahbso(6));
|
|
|
end generate;
|
|
|
nobpromgen : if CFG_AHBROMEN = 0 generate
|
|
|
ahbso(6) <= ahbs_none;
|
|
|
end generate;
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- AHB RAM ----------------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
ahbramgen : if CFG_AHBRAMEN = 1 generate
|
|
|
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
|
|
|
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
|
|
|
port map (rstn, clkm, ahbsi, ahbso(3));
|
|
|
end generate;
|
|
|
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- Drive unused bus elements ---------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+5) to NAHBMST-1 generate
|
|
|
ahbmo(i) <= ahbm_none;
|
|
|
end generate;
|
|
|
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
|
|
|
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
|
|
|
|
|
|
-- resoutn <= rstn;
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
|
--- Boot message ----------------------------------------------------
|
|
|
-----------------------------------------------------------------------
|
|
|
|
|
|
-- pragma translate_off
|
|
|
x : report_version
|
|
|
generic map (
|
|
|
msg1 => "LEON3 Demonstration design for Digilent Spartan3E Eval board",
|
|
|
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
|
|
|
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
|
|
|
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
|
|
|
mdel => 1
|
|
|
);
|
|
|
-- pragma translate_on
|
|
|
|
|
|
end rtl;
|
|
|
|
