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added re-run option to LFR filter random ram init test.
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config.help
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Prompt for target technology
CONFIG_SYN_INFERRED
Selects the target technology for memory and pads.
The following are available:
- Inferred: Generic FPGA or ASIC targets if your synthesis tool
is capable of inferring RAMs and pads automatically.
- Actel ProAsic/P/3, IGLOO and Axcelerator FPGAs
- Aeroflex UT25CRH Rad-Hard 0.25 um CMOS
- Altera: Most Altera FPGA families
- Altera-Stratix: Altera Stratix FPGA family
- Altera-StratixII: Altera Stratix-II FPGA family
- ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
- IHP25: IHP 0.25 um CMOS
- IHP25RH: IHP Rad-Hard 0.25 um CMOS
- Lattice : EC/ECP/XP FPGAs
- Quicklogic : Eclipse/E/II FPGAs
- UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
- Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries
- Xilinx-Spartan3E: Xilinx Spartan3E libraries
- Xilinx-Virtex/E: Xilinx Virtex/E libraries
- Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries
Ram library
CONFIG_MEM_VIRAGE
Select RAM generators for ASIC targets.
Infer ram
CONFIG_SYN_INFER_RAM
Say Y here if you want the synthesis tool to infer your
RAM automatically. Say N to directly instantiate technology-
specific RAM cells for the selected target technology package.
Infer pads
CONFIG_SYN_INFER_PADS
Say Y here if you want the synthesis tool to infer pads.
Say N to directly instantiate technology-specific pads from
the selected target technology package.
No async reset
CONFIG_SYN_NO_ASYNC
Say Y here if you disable asynchronous reset in some of the IP cores.
Might be necessary if the target library does not have cells with
asynchronous set/reset.
Scan support
CONFIG_SYN_SCAN
Say Y here to enable scan support in some cores. This will enable
the scan support generics where available and add logic to make
the design testable using full-scan.
Use Virtex CLKDLL for clock synchronisation
CONFIG_CLK_INFERRED
Certain target technologies include clock generators to scale or
phase-adjust the system and SDRAM clocks. This is currently supported
for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you
can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2),
the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL
(Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred'
option to skip a clock generator.
Clock multiplier
CONFIG_CLK_MUL
When using the Xilinx DCM or Altera ALTPLL, the system clock can
be multiplied with a factor of 2 - 32, and divided by a factor of
1 - 32. This makes it possible to generate almost any desired
processor frequency. When using the Xilinx CLKDLL generator,
the resulting frequency scale factor (mul/div) must be one of
1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
WARNING: The resulting clock must be within the limits specified
by the target FPGA family.
Clock divider
CONFIG_CLK_DIV
When using the Xilinx DCM or Altera ALTPLL, the system clock can
be multiplied with a factor of 2 - 32, and divided by a factor of
1 - 32. This makes it possible to generate almost any desired
processor frequency. When using the Xilinx CLKDLL generator,
the resulting frequency scale factor (mul/div) must be one of
1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
WARNING: The resulting clock must be within the limits specified
by the target FPGA family.
Output clock divider
CONFIG_OCLK_DIV
When using the Proasic3 PLL, the system clock is generated by three
parameters: input clock multiplication, input clock division and
output clock division. Only certain values of these parameters
are allowed, but unfortunately this is not documented by Actel.
To find the correct values, run the Libero Smartgen tool and
insert you desired input and output clock frequencies in the
Static PLL configurator. The mul/div factors can then be read
out from tool.
Output clock divider, 2nd clock
CONFIG_OCLKB_DIV
See help for 'Ouput division factor'. Set this to 0 to disable the
second clock output.
Output clock divider, 3rd clock
CONFIG_OCLKC_DIV
See help for 'Ouput division factor'. Set this to 0 to disable the
third clock output.
System clock multiplier
CONFIG_CLKDLL_1_2
The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0,
or 2.0. Useful when the target board has an oscillator with a too high
(or low) frequency for your design. The divided clock will be used as the
main clock for the whole processor (except PCI and ethernet clocks).
System clock multiplier
CONFIG_DCM_2_3
The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
range of factors. Useful when the target board has an oscillator with a
too high (or low) frequency for your design. The divided clock will
be used as the main clock for the whole processor (except PCI and
ethernet clocks). NOTE: the resulting frequency must be at least
24 MHz or the DCM and ALTDLL might not work.
Enable CLKDLL for PCI clock
CONFIG_PCI_CLKDLL
Say Y here to re-synchronize the PCI clock using a
Virtex BUFGDLL macro. Will improve PCI clock-to-output
delays on the expense of input-setup requirements.
Use PCI clock system clock
CONFIG_PCI_SYSCLK
Say Y here to the PCI clock to generate the system clock.
The PCI clock can be scaled using the DCM or CLKDLL to
generate a suitable processor clock.
External SDRAM clock feedback
CONFIG_CLK_NOFB
Say Y here to disable the external clock feedback to synchronize the
SDRAM clock. This option is necessary if your board or design does not
have an external clock feedback that is connected to the pllref input
of the clock generator.
Number of processors
CONFIG_PROC_NUM
The number of processor cores. The LEON3MP design can accomodate
up to 4 LEON3 processor cores. Use 1 unless you know what you are
doing ...
Number of SPARC register windows
CONFIG_IU_NWINDOWS
The SPARC architecture (and LEON) allows 2 - 32 register windows.
However, any number except 8 will require that you modify and
recompile your run-time system or kernel. Unless you know what
you are doing, use 8.
SPARC V8 multiply and divide instruction
CONFIG_IU_V8MULDIV
If you say Y here, the SPARC V8 multiply and divide instructions
will be implemented. The instructions are: UMUL, UMULCC, SMUL,
SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
integer multiplications and divisions, significant performance
increase can be achieved. Emulated floating-point operations will
also benefit from this option.
By default, the gcc compiler does not emit multiply or divide
instructions and your code must be compiled with -mv8 to see any
performance increase. On the other hand, code compiled with -mv8
will generate an illegal instruction trap when executed on processors
with this option disabled.
The divider consumes approximately 2 kgates, the multiplier 6 kgates.
Multiplier latency
CONFIG_IU_MUL_LATENCY_2
Implementation options for the integer multiplier.
Type Implementation issue-rate/latency
2-clocks 32x32 pipelined multiplier 1/2
4-clocks 16x16 standard multiplier 4/4
5-clocks 16x16 pipelined multiplier 4/5
Multiplier latency
CONFIG_IU_MUL_MAC
If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
instructions will be enabled. The instructions implement a
single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
The details of these instructions can be found in the LEON manual,
This option is only available when 16x16 multiplier is used.
Branch prediction
CONFIG_IU_BP
Enabling branch prediction will improve performance with
up to 20%, depending on application. The timing and area
overhead are minor, so it is recommended to always enable
this option.
Single vector trapping
CONFIG_IU_SVT
Single-vector trapping is a SPARC V8e option to reduce code-size
in small applications. If enabled, the processor will jump to
the address of trap 0 (tt = 0x00) for all traps. No trap table
is then needed. The trap type is present in %psr.tt and must
be decoded by the O/S. Saves 4 Kbyte of code, but increases
trap and interrupt overhead. Currently, the only O/S supporting
this option is eCos. To enable SVT, the O/S must also set bit 13
in %asr17.
Load latency
CONFIG_IU_LDELAY
Defines the pipeline load delay (= pipeline cycles before the data
from a load instruction is available for the next instruction).
One cycle gives best performance, but might create a critical path
on targets with slow (data) cache memories. A 2-cycle delay can
improve timing but will reduce performance with about 5%.
Reset address
CONFIG_IU_RSTADDR
By default, a SPARC processor starts execution at address 0.
With this option, any 4-kbyte aligned reset start address can be
choosen. Keep at 0 unless you really know what you are doing.
No tagged arithmetic
CONFIG_NOTAG
Say Y here to disable tagged arithmetic and the CASA instructions.
This will save some area in minimal systems that do not need
these features.
Power-down
CONFIG_PWD
Say Y here to enable the power-down feature of the processor.
Might reduce the maximum frequency slightly on FPGA targets.
For details on the power-down operation, see the LEON3 manual.
Hardware watchpoints
CONFIG_IU_WATCHPOINTS
The processor can have up to 4 hardware watchpoints, allowing to
create both data and instruction breakpoints at any memory location,
also in PROM. Each watchpoint will use approximately 500 gates.
Use 0 to disable the watchpoint function.
Floating-point enable
CONFIG_FPU_ENABLE
Say Y here to enable the floating-point interface for the MEIKO
or GRFPU. Note that no FPU's are provided with the GPL version
of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial
cores and must be obtained separately.
FPU selection
CONFIG_FPU_GRFPU
Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun
Meiko FPU core. All cores are fully IEEE-754 compatible and support
all SPARC FPU instructions.
GRFPU Multiplier
CONFIG_FPU_GRFPU_INFMUL
On FPGA targets choose inferred multiplier. For ASIC implementations
choose between Synopsys Design Ware (DW) multiplier or Module
Generator (ModGen) multiplier. The DW multiplier gives better results
(smaller area and better timing) but requires a DW license.
The ModGen multiplier is part of GRLIB and does not require a license.
The Technology Specific multiplier option selects a pre-designed
multiplier using technology specific macrocells when available, else
an inferred multiplier is used.
Shared GRFPU
CONFIG_FPU_GRFPU_SH
If enabled multiple CPU cores will share one GRFPU.
GRFPC Configuration
CONFIG_FPU_GRFPC0
Configures the GRFPU-LITE controller.
In simple configuration controller executes FP instructions
in parallel with integer instructions. FP operands are fetched
in the register file stage and the result is written in the write
stage. This option uses least area resources.
Data forwarding configuration gives ~ 10 % higher FP performance than
the simple configuration by adding data forwarding between the pipeline
stages.
Non-blocking controller allows FP load and store instructions to
execute in parallel with FP instructions. The performance increase is
~ 20 % for FP applications. This option uses most logic resources and
is suitable for ASIC implementations.
Floating-point netlist
CONFIG_FPU_NETLIST
Say Y here to use a VHDL netlist of the GRFPU-Lite. This is
only available in certain versions of grlib.
Enable Instruction cache
CONFIG_ICACHE_ENABLE
The instruction cache should always be enabled to allow
maximum performance. Some low-end system might want to
save area and disable the cache, but this will reduce
the performance with a factor of 2 - 3.
Enable Data cache
CONFIG_DCACHE_ENABLE
The data cache should always be enabled to allow
maximum performance. Some low-end system might want to
save area and disable the cache, but this will reduce
the performance with a factor of 2 at least.
Instruction cache associativity
CONFIG_ICACHE_ASSO1
The instruction cache can be implemented as a multi-set cache with
1 - 4 sets. Higher associativity usually increases the cache hit
rate and thereby the performance. The downside is higher power
consumption and increased gate-count for tag comparators.
Note that a 1-set cache is effectively a direct-mapped cache.
Instruction cache set size
CONFIG_ICACHE_SZ1
The size of each set in the instuction cache (kbytes). Valid values
are 1 - 64 in binary steps. Note that the full range is only supported
by the generic and virtex2 targets. Most target packages are limited
to 2 - 16 kbyte. Large set size gives higher performance but might
affect the maximum frequency (on ASIC targets). The total instruction
cache size is the number of set multiplied with the set size.
Instruction cache line size
CONFIG_ICACHE_LZ16
The instruction cache line size. Can be set to either 16 or 32
bytes per line. Instruction caches typically benefit from larger
line sizes, but on small caches it migh be better with 16 bytes/line
to limit eviction miss rate.
Instruction cache replacement algorithm
CONFIG_ICACHE_ALGORND
Cache replacement algorithm for caches with 2 - 4 sets. The 'random'
algorithm selects the set to evict randomly. The least-recently-replaced
(LRR) algorithm evicts the set least recently replaced. The least-
recently-used (LRU) algorithm evicts the set least recently accessed.
The random algorithm uses a simple 1- or 2-bit counter to select
the eviction set and has low area overhead. The LRR scheme uses one
extra bit in the tag ram and has therefore also low area overhead.
However, the LRR scheme can only be used with 2-set caches. The LRU
scheme has typically the best performance but also highest area overhead.
A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops
per line, and a 4-set LRU uses 5 flip-flops per line to store the access
history.
Instruction cache locking
CONFIG_ICACHE_LOCK
Say Y here to enable cache locking in the instruction cache.
Locking can be done on cache-line level, but will increase the
width of the tag ram with one bit. If you don't know what
locking is good for, it is safe to say N.
Data cache associativity
CONFIG_DCACHE_ASSO1
The data cache can be implemented as a multi-set cache with
1 - 4 sets. Higher associativity usually increases the cache hit
rate and thereby the performance. The downside is higher power
consumption and increased gate-count for tag comparators.
Note that a 1-set cache is effectively a direct-mapped cache.
Data cache set size
CONFIG_DCACHE_SZ1
The size of each set in the data cache (kbytes). Valid values are
1 - 64 in binary steps. Note that the full range is only supported
by the generic and virtex2 targets. Most target packages are limited
to 2 - 16 kbyte. A large cache gives higher performance but the
data cache is timing critical an a too large setting might affect
the maximum frequency (on ASIC targets). The total data cache size
is the number of set multiplied with the set size.
Data cache line size
CONFIG_DCACHE_LZ16
The data cache line size. Can be set to either 16 or 32 bytes per
line. A smaller line size gives better associativity and higher
cache hit rate, but requires a larger tag memory.
Data cache replacement algorithm
CONFIG_DCACHE_ALGORND
See the explanation for instruction cache replacement algorithm.
Data cache locking
CONFIG_DCACHE_LOCK
Say Y here to enable cache locking in the data cache.
Locking can be done on cache-line level, but will increase the
width of the tag ram with one bit. If you don't know what
locking is good for, it is safe to say N.
Data cache snooping
CONFIG_DCACHE_SNOOP
Say Y here to enable data cache snooping on the AHB bus. Is only
useful if you have additional AHB masters such as the DSU or a
target PCI interface. Note that the target technology must support
dual-port RAMs for this option to be enabled. Dual-port RAMS are
currently supported on Virtex/2, Virage and Actel targets.
Data cache snooping implementation
CONFIG_DCACHE_SNOOP_FAST
The default snooping implementation is 'slow', which works if you
don't have AHB slaves in cacheable areas capable of zero-waitstates
non-sequential write accesses. Otherwise use 'fast' and suffer a
few kgates extra area. This option is currently only needed in
multi-master systems with the SSRAM or DDR memory controllers.
Separate snoop tags
CONFIG_DCACHE_SNOOP_SEPTAG
Enable a separate memory to store the data tags used for snooping.
This is necessary when snooping support is wanted in systems
with MMU, typically for SMP systems. In this case, the snoop
tags will contain the physical tag address while the normal
tags contain the virtual tag address. This option can also be
together with the 'fast snooping' option to enable snooping
support on technologies without dual-port RAMs. In such case,
the snoop tag RAM will be implemented using a two-port RAM.
Fixed cacheability map
CONFIG_CACHE_FIXED
If this variable is 0, the cacheable memory regions are defined
by the AHB plug&play information (default). To overriden the
plug&play settings, this variable can be set to indicate which
areas should be cached. The value is treated as a 16-bit hex value
with each bit defining if a 256 Mbyte segment should be cached or not.
The right-most (LSB) bit defines the cacheability of AHB address
0 - 256 MByte, while the left-most bit (MSB) defines AHB address
3840 - 4096 MByte. If the bit is set, the corresponding area is
cacheable. A value of 00F3 defines address 0 - 0x20000000 and
0x40000000 - 0x80000000 as cacheable.
Local data ram
CONFIG_DCACHE_LRAM
Say Y here to add a local ram to the data cache controller.
Accesses to the ram (load/store) will be performed at 0 waitstates
and store data will never be written back to the AHB bus.
Size of local data ram
CONFIG_DCACHE_LRAM_SZ1
Defines the size of the local data ram in Kbytes. Note that most
technology libraries do not support larger rams than 16 Kbyte.
Start address of local data ram
CONFIG_DCACHE_LRSTART
Defines the 8 MSB bits of start address of the local data ram.
By default set to 8f (start address = 0x8f000000), but any value
(except 0) is possible. Note that the local data ram 'shadows'
a 16 Mbyte block of the address space.
MMU enable
CONFIG_MMU_ENABLE
Say Y here to enable the Memory Management Unit.
MMU split icache/dcache table lookaside buffer
CONFIG_MMU_COMBINED
Select "combined" for a combined icache/dcache table lookaside buffer,
"split" for a split icache/dcache table lookaside buffer
MMU tlb replacement scheme
CONFIG_MMU_REPARRAY
Select "LRU" to use the "least recently used" algorithm for TLB
replacement, or "Increment" for a simple incremental replacement
scheme.
Combined i/dcache tlb
CONFIG_MMU_I2
Select the number of entries for the instruction TLB, or the
combined icache/dcache TLB if such is used.
Split tlb, dcache
CONFIG_MMU_D2
Select the number of entries for the dcache TLB.
Fast writebuffer
CONFIG_MMU_FASTWB
Only selectable if split tlb is enabled. In case fast writebuffer is
enabled the tlb hit will be made concurrent to the cache hit. This
leads to higher store performance, but increased power and area.
MMU pagesize
CONFIG_MMU_PAGE_4K
The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the
cache way size to 4 Kbyte, and total data cache size to 16 Kbyte,
when the MMU is used. To increase the maximum data cache size,
the MMU pages size can be increased to up 32 Kbyte. This will
give a maximum data cache size of 128 Kbyte.
Note that an MMU page size different than 4 Kbyte will require
a special linux tool-chain if glibc is used. If you don't know
what you are doing, stay with 4 Kbyte ...
DSU enable
CONFIG_DSU_ENABLE
The debug support unit (DSU) allows non-intrusive debugging and tracing
of both executed instructions and AHB transfers. If you want to enable
the DSU, say Y here and select the configuration below.
Trace buffer enable
CONFIG_DSU_TRACEBUF
Say Y to enable the trace buffer. The buffer is not necessary for
debugging, only for tracing instructions and data transfers.
Enable instruction tracing
CONFIG_DSU_ITRACE
If you say Y here, an instruction trace buffer will be implemented
in each processor. The trace buffer will trace executed instructions
and their results, and place them in a circular buffer. The buffer
can be read out by any AHB master, and in particular by the debug
communication link.
Size of trace buffer
CONFIG_DSU_ITRACESZ1
Select the buffer size (in kbytes) for the instruction trace buffer.
Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
need 2 kbyte.
Enable AHB tracing
CONFIG_DSU_ATRACE
If you say Y here, an AHB trace buffer will be implemented in the
debug support unit processor. The AHB buffer will trace all transfers
on the AHB bus and save them in a circular buffer. The trace buffer
can be read out by any AHB master, and in particular by the debug
communication link.
Size of trace buffer
CONFIG_DSU_ATRACESZ1
Select the buffer size (in kbytes) for the AHB trace buffer.
Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
need 2 kbyte.
LEON3FT enable
CONFIG_LEON3FT_EN
Say Y here to use the fault-tolerant LEON3FT core instead of the
standard non-FT LEON3.
IU Register file protection
CONFIG_IUFT_NONE
Select the FT implementation in the LEON3FT integer unit
register file. The options include parity, parity with
sparing, 7-bit BCH and TMR.
FPU Register file protection
CONFIG_FPUFT_EN
Say Y to enable SEU protection of the FPU register file.
The GRFPU will be protected using 8-bit parity without restart, while
the GRFPU-Lite will be protected with 4-bit parity with restart. If
disabled the FPU register file will be implemented using flip-flops.
Cache memory error injection
CONFIG_RF_ERRINJ
Say Y here to enable error injection in to the IU/FPU regfiles.
Affects only simulation.
Cache memory protection
CONFIG_CACHE_FT_EN
Enable SEU error-correction in the cache memories.
Cache memory error injection
CONFIG_CACHE_ERRINJ
Say Y here to enable error injection in to the cache memories.
Affects only simulation.
Leon3ft netlist
CONFIG_LEON3_NETLIST
Say Y here to use a VHDL netlist of the LEON3FT. This is
only available in certain versions of grlib.
IU assembly printing
CONFIG_IU_DISAS
Enable printing of executed instructions to the console.
IU assembly printing in netlist
CONFIG_IU_DISAS_NET
Enable printing of executed instructions to the console also
when simulating a netlist. NOTE: with this option enabled, it
will not be possible to pass place&route.
32-bit program counters
CONFIG_DEBUG_PC32
Since the LSB 2 bits of the program counters always are zero, they are
normally not implemented. If you say Y here, the program counters will
be implemented with full 32 bits, making debugging of the VHDL model
much easier. Turn of this option for synthesis or you will be wasting
area.
CONFIG_AHB_DEFMST
Sets the default AHB master (see AMBA 2.0 specification for definition).
Should not be set to a value larger than the number of AHB masters - 1.
For highest processor performance, leave it at 0.
Default AHB master
CONFIG_AHB_RROBIN
Say Y here to enable round-robin arbitration of the AHB bus. A N will
select fixed priority, with the master with the highest bus index having
the highest priority.
Support AHB split-transactions
CONFIG_AHB_SPLIT
Say Y here to enable AHB split-transaction support in the AHB arbiter.
Unless you actually have an AHB slave that can generate AHB split
responses, say N and save some gates.
Default AHB master
CONFIG_AHB_IOADDR
Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined
in the plug&play extentions of the AMBA bus. Should be kept to FFF
unless you really know what you are doing.
APB bridge address
CONFIG_APB_HADDR
Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
kept at 800 for software compatibility.
AHB monitor
CONFIG_AHB_MON
Say Y to enable the AHB bus monitor. The monitor will check for
illegal AHB transactions during simulation. It has no impact on
synthesis.
Report AHB errors
CONFIG_AHB_MONERR
Print out detected AHB violations on console.
Report AHB warnings
CONFIG_AHB_MONWAR
Print out detected AHB warnings on console.
Write trace to console
CONFIG_AHB_DTRACE
Say yes here to write a trace of all AHB transfers to the
simulator console. Has not impact on final netlist.
DSU enable
CONFIG_DSU_UART
Say Y to enable the AHB uart (serial-to-AHB). This is the most
commonly used debug communication link.
JTAG Enable
CONFIG_DSU_JTAG
Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done
with GRMON through the boards JTAG chain at speeds of up to 800 kbits/s.
The TAP controller can be implemented in custom macros on
Altera, Actel Proasic/3 and Xilinx devices. The commercial
GRLIB also includes a generic TAP controller in VHDL.
Supported JTAG cables are Xilinx Parallel Cable III and IV,
Xilinx Platform cables (USB), and Altera parallel and USB cables,
Amontech JTAG key, various FTDI chip based USB/JTAG devices, and
Actel Flash Pro 3/4 cable.
Ethernet DSU enable
CONFIG_DSU_ETH
Say Y to enable the Ethernet Debug Communication Link (EDCL). The link
provides a DSU gateway between ethernet and the AHB bus. Debugging is
done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must
enable the GRETH Ethernet MAC for this option to become active.
Size of EDCL trace buffer
CONFIG_DSU_ETHSZ1
Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is
usually enough, while a larger buffer will increase the transfer rate.
When operating at 100 Mbit, use a buffer size of at least 8 kbyte for
maximum throughput.
MSB IP address
CONFIG_DSU_IPMSB
Set the MSB 16 bits of the IP address of the EDCL.
LSB IP address
CONFIG_DSU_IPLSB
Set the LSB 16 bits of the IP address of the EDCL.
MSB ethernet address
CONFIG_DSU_ETHMSB
Set the MSB 24 bits of the ethernet address of the EDCL.
LSB ethernet address
CONFIG_DSU_ETHLSB
Set the LSB 24 bits of the ethernet address of the EDCL.
Programmable MAC/IP address
CONFIG_DSU_ETH_PROG
Say Y to make the LSB 4 bits of the EDCL MAC and IP address
configurable using the ethi.edcladdr inputs.
Leon2 memory controller
CONFIG_MCTRL_LEON2
Say Y here to enable the LEON2 memory controller. The controller
can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
and SRAM is programmable to 8-, 16- or 32-bits.
8-bit memory support
CONFIG_MCTRL_8BIT
If you say Y here, the PROM/SRAM memory controller will support
8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
Say N to save a few hundred gates.
16-bit memory support
CONFIG_MCTRL_16BIT
If you say Y here, the PROM/SRAM memory controller will support
16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
Say N to save a few hundred gates.
Write strobe feedback
CONFIG_MCTRL_WFB
If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
be used to enable the data bus drivers during write cycles. This
will guarantee that the data is still valid on the rising edge of
the write strobe. If you say N, the write strobes and the data bus
drivers will be clocked on the rising edge, potentially creating
a hold time problem in external memory or I/O. However, in all
practical cases, there is enough capacitance in the data bus lines
to keep the value stable for a few (many?) nano-seconds after the
buffers have been disabled, making it safe to say N and remove a
combinational path in the netlist that might be difficult to
analyze.
Write strobe feedback
CONFIG_MCTRL_5CS
If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
be enabled. If you don't intend to use it, say N and save some gates.
SDRAM controller enable
CONFIG_MCTRL_SDRAM
Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
intend to use SDRAM, say N and save about 1 kgates.
SDRAM controller inverted clock
CONFIG_MCTRL_SDRAM_INVCLK
If you say Y here, the SDRAM controller output signals will be delayed
with 1/2 clock in respect to the SDRAM clock. This will allow the used
of an SDRAM clock which in not strictly in phase with the internal
clock. This option will limit the SDRAM frequency to 40 - 50 MHz.
On FPGA targets without SDRAM clock synchronizations through PLL/DLL,
say Y. On ASIC targets, say N and tell your foundry to balance the
SDRAM clock output.
SDRAM separate address buses
CONFIG_MCTRL_SDRAM_SEPBUS
Say Y here if your SDRAM is connected through separate address
and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.
64-bit data bus
CONFIG_MCTRL_SDRAM_BUS64
Say Y here to enable 64-bit SDRAM data bus.
Page burst enable
CONFIG_MCTRL_PAGE
Say Y here to enable SDRAM page burst operation. This will implement
read operations using page bursts rather than 8-word bursts and save
about 500 gates (100 LUTs). Note that not all SDRAM supports page
burst, so use this option with care.
Programmable page burst enable
CONFIG_MCTRL_PROGPAGE
Say Y here to enable programmable SDRAM page burst operation. This
will allow to dynamically enable/disable page burst by setting
bit 17 in MCFG2.
SDRAM controller enable
CONFIG_DDRSP
Say Y here to enabled a 16-bit DDR266 SDRAM controller.
Power-on init
CONFIG_DDRSP_INIT
Say Y here to enable the automatic DDR initialization sequence.
If disabled, the sequencemust be performed in software before
the DDR can be used. If unsure, say Y.
Memory frequency
CONFIG_DDRSP_FREQ
Enter the frequency of the DDR clock (in MHz). The value is
typically between 80 - 133, depending on system configuration.
Some template design (such as the leon3-avnet-eval-lx25)
calculate this value automatically and this value is not used.
Column bits
CONFIG_DDRSP_COL
Select the number of colomn address bits of the DDR memory.
Typical values are 8 - 11. Only needed when automatic DDR
initialisation is choosen. The column size can always be
programmed by software as well.
Chip select size
CONFIG_DDRSP_MBYTE
Select the memory size (Mbytes) that each chip select should decode.
Only needed when automatic DDR initialisation is choosen. The chip
select size can always be programmed by software as well.
Read clock phase shift
CONFIG_DDRSP_RSKEW
On Xilinx targets, the read clock is de-skewed and phase-shifted
using a DCM connected to the feed-back clock input. On some boards,
the de-skewing does not work perfectly, and some extra phase shifting
must be added manually. The entered value is set to the PHASE_SHIFT
generic on the Xilinx DCM. The Digilent Sparten3E-1600 board typically
needs a value of 35, while the Avnet Virtex4 Eval board needs -90.
For Altera CycloneIII, the entered value is set to the PHASE_SHIFT of
the PLL in ps (e.g 2500 for 90' shift in 100MHz)
On-chip rom
CONFIG_AHBROM_ENABLE
Say Y here to add a block on on-chip rom to the AHB bus. The ram
provides 0-waitstates read access, burst support, and 8-, 16-
and 32-bit data size. The rom will be syntheised into block rams
on Xilinx and Altera FPGA devices, and into gates on ASIC
technologies. GRLIB includes a utility to automatically create
the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
documentation for details.
On-chip rom address
CONFIG_AHBROM_START
Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
a 1 Mbyte slot at the selected address. Default is 000, corresponding
to AHB address 0x00000000. When address 0x0 is selected, the rom area
of any other memory controller is set to 0x10000000 to avoid conflicts.
Enable pipeline register for on-chip rom
CONFIG_AHBROM_PIPE
Say Y here to add a data pipeline register to the on-chip rom.
This should be done when the rom is implemenented in (ASIC) gates,
or in logic cells on FPGAs. Do not use this option when the rom is
implemented in block rams. If enabled, the rom will operate with
one waitstate.
On-chip ram
CONFIG_AHBRAM_ENABLE
Say Y here to add a block on on-chip ram to the AHB bus. The ram
provides 0-waitstates read access and 0/1 waitstates write access.
All AHB burst types are supported, as well as 8-, 16- and 32-bit
data size.
On-chip ram size
CONFIG_AHBRAM_SZ1
Set the size of the on-chip AHB ram. The ram is infered/instantiated
as four byte-wide ram slices to allow byte and half-word write
accesses. It is therefore essential that the target package can
infer byte-wide rams. This is currently supported on the generic,
virtex, virtex2, proasic and axellerator targets.
On-chip ram address
CONFIG_AHBRAM_START
Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
a 1 Mbyte slot at the selected address. Default is A00, corresponding
to AHB address 0xA0000000.
Gaisler Ethernet MAC enable
CONFIG_GRETH_ENABLE
Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has
one AHB master interface to read and write packets to memory, and one
APB slave interface for accessing the control registers.
Gaisler Ethernet 1G MAC enable
CONFIG_GRETH_GIGA
Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC .
The 1G MAC is only available in the commercial version of GRLIB,
so do NOT enable it if you are using the GPL version.
CONFIG_GRETH_FIFO4
Set the depth of the receive and transmit FIFOs in the MAC core.
The MAC core will perform AHB burst read/writes with half the
size of the FIFO depth.
UART1 enable
CONFIG_UART1_ENABLE
Say Y here to enable UART1, or the console UART. This is needed to
get any print-out from LEON3 systems regardless of operating system.
UART1 FIFO
CONFIG_UA1_FIFO1
The UART has configurable transmitt and receive FIFO's, which can
be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
maximum throughput.
LEON3 interrupt controller
CONFIG_IRQ3_ENABLE
Say Y here to enable the LEON3 interrupt controller. This is needed
if you want to be able to receive interrupts. Operating systems like
Linux, RTEMS and eCos needs this option to be enabled. If you intend
to use the Bare-C run-time and not use interrupts, you could disable
the interrupt controller and save about 500 gates.
LEON3 interrupt controller broadcast
CONFIG_IRQ3_BROADCAST_ENABLE
If enabled the broadcast register is used to determine which
interrupt should be sent to all cpus instead of just the first
one that consumes it.
Secondary interrupts
CONFIG_IRQ3_SEC
The interrupt controller handles 15 interrupts by default (1 - 15).
These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F),
and AMBA interrupts 1 - 15. This option will enable 16 additional
(secondary) interrupts, corresponding to AMBA interrupts 16 - 31.
The secondary interrupts will be multiplexed onto one of the first
15 interrupts. The total number of handled interrupts can then
be up to 30 (14 primary and 16 secondary).
Number of interrupts
CONFIG_IRQ3_NSEC
Defines which of the first 15 interrupts should be used for the
secondary (16 - 31) interrupts. Interrupt 15 should be avoided
since it is not maskable by the processor.
Timer module enable
CONFIG_GPT_ENABLE
Say Y here to enable the Modular Timer Unit. The timer unit consists
of one common scaler and up to 7 independent timers. The timer unit
is needed for Linux, RTEMS, eCos and the Bare-C run-times.
Timer module enable
CONFIG_GPT_NTIM
Set the number of timers in the timer unit (1 - 7).
Scaler width
CONFIG_GPT_SW
Set the width if the common pre-scaler (2 - 16 bits). The scaler
is used to divide the system clock down to 1 MHz, so 8 bits should
be sufficient for most implementations (allows clocks up to 256 MHz).
Timer width
CONFIG_GPT_TW
Set the width if the timers (2 - 32 bits). 32 bits is recommended
for the Bare-C run-time, lower values (e.g. 16 bits) can work with
RTEMS and Linux.
Timer Interrupt
CONFIG_GPT_IRQ
Set the interrupt number for the first timer. Remaining timers will
have incrementing interrupts, unless the separate-interrupts option
below is disabled.
Watchdog enable
CONFIG_GPT_WDOGEN
Say Y here to enable the watchdog functionality in the timer unit.
Watchdog time-out value
CONFIG_GPT_WDOG
This value will be loaded in the watchdog timer at reset.
GPIO port
CONFIG_GRGPIO_ENABLE
Say Y here to enable a general purpose I/O port. The port can be
configured from 1 - 32 bits, whith each port signal individually
programmable as input or output. The port signals can also serve
as interrupt inputs.
GPIO port witdth
CONFIG_GRGPIO_WIDTH
Number of bits in the I/O port. Must be in the range of 1 - 32.
GPIO interrupt mask
CONFIG_GRGPIO_IMASK
The I/O port interrupt mask defines which bits in the I/O port
should be able to create an interrupt.
Text-mode VGA
CONFIG_VGA_ENABLE
Say Y here to enable a simple text-mode VGA controller. The controller
generate 48x36 characters on a 640x480 pixel screen. The pixel clock
is 25 MHz.
SVGA frame buffer
CONFIG_SVGA_ENABLE
Say Y here to enable a graphical frame buffer. The frame buffer
can be configured up to 1024x768 pixels and 8-, 16- or 32-bit
colour depth.
PS2 KBD interface
CONFIG_KBD_ENABLE
Say Y here to enable a PS/2 keyboard or mouse interface.
UART debugging
CONFIG_DEBUG_UART
During simulation, the output from the UARTs is printed on the
simulator console. Since the ratio between the system clock and
UART baud-rate is quite high, simulating UART output will be very
slow. If you say Y here, the UARTs will print a character as soon
as it is stored in the transmitter data register. The transmitter
ready flag will be permanently set, speeding up simulation. However,
the output on the UART tx line will be garbled. Has not impact on
synthesis, but will cause the LEON test bench to fail.
FPU register tracing
CONFIG_DEBUG_FPURF
If you say Y here, all writes to the floating-point unit register file
will be printed on the simulator console.