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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY std;
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use std.textio.all;
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ENTITY data_read_with_timer IS
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GENERIC (
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input_file_name : STRING := "input_data_2.txt";
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NB_CHAR_PER_DATA : INTEGER := 4;
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NB_CYCLE_TIMER : INTEGER := 1024
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);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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end_of_file : OUT STD_LOGIC;
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data_out_val : OUT STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0)
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);
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END;
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ARCHITECTURE beh OF data_read_with_timer IS
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COMPONENT data_read
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GENERIC (
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input_file_name : STRING;
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NB_CHAR_PER_DATA : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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read_new_data : IN STD_LOGIC;
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end_of_file : OUT STD_LOGIC;
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data_out_val : OUT STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));
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END COMPONENT;
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SIGNAL nb_cycle_counter : INTEGER;
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SIGNAL read_new_data : STD_LOGIC;
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BEGIN -- beh
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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nb_cycle_counter <= 0;
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read_new_data <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF nb_cycle_counter < NB_CYCLE_TIMER-1 THEN
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nb_cycle_counter <= nb_cycle_counter + 1;
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read_new_data <= '0';
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ELSE
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nb_cycle_counter <= 0;
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read_new_data <= '1';
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END IF;
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END IF;
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END PROCESS;
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data_read_1: data_read
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GENERIC MAP (
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input_file_name => input_file_name,
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NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)
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PORT MAP (
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clk => clk,
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read_new_data => read_new_data,
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end_of_file => end_of_file,
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data_out_val => data_out_val,
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data_out => data_out);
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END beh;
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