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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity DEMUX is
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generic(
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Data_sz : integer range 1 to 32 := 16);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Read : in std_logic_vector(4 downto 0);
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Load : in std_logic;
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EmptyF0 : in std_logic_vector(4 downto 0);
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EmptyF1 : in std_logic_vector(4 downto 0);
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EmptyF2 : in std_logic_vector(4 downto 0);
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DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
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DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
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WorkFreq : out std_logic_vector(1 downto 0);
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Read_DEMUX : out std_logic_vector(14 downto 0);
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Empty : out std_logic_vector(4 downto 0);
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Data : out std_logic_vector((5*Data_sz)-1 downto 0)
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);
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end entity;
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architecture ar_DEMUX of DEMUX is
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type etat is (eX,e0,e1,e2,e3);
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signal ect : etat;
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signal load_reg : std_logic;
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constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
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signal Countf0 : integer;
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signal Countf1 : integer;
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signal i : integer;
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begin
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process(clk,rstn)
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begin
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if(rstn='0')then
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ect <= e0;
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load_reg <= '0';
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Countf0 <= 0;
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Countf1 <= 0;
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i <= 0;
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elsif(clk'event and clk='1')then
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load_reg <= Load;
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case ect is
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when e0 =>
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if(load_reg = '1' and Load = '0')then
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if(Countf0 = 24)then
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Countf0 <= 0;
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ect <= e1;
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else
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Countf0 <= Countf0 + 1;
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ect <= e0;
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end if;
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end if;
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when e1 =>
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if(load_reg = '1' and Load = '0')then
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if(Countf1 = 74)then
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Countf1 <= 0;
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ect <= e2;
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else
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Countf1 <= Countf1 + 1;
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if(i=4)then
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i <= 0;
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ect <= e0;
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else
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i <= i+1;
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ect <= e1;
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end if;
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end if;
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end if;
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when e2 =>
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if(load_reg = '1' and Load = '0')then
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if(i=4)then
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i <= 0;
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ect <= e0;
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else
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i <= i+1;
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ect <= e2;
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end if;
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end if;
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when others =>
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null;
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end case;
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end if;
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end process;
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with ect select
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Empty <= EmptyF0 when e0,
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EmptyF1 when e1,
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EmptyF2 when e2,
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(others => '1') when others;
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with ect select
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Data <= DataF0 when e0,
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DataF1 when e1,
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DataF2 when e2,
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(others => '0') when others;
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with ect select
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Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0,
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Dummy_Read & Read & Dummy_Read when e1,
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Read & Dummy_Read & Dummy_Read when e2,
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(others => '1') when others;
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with ect select
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WorkFreq <= "01" when e0,
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"10" when e1,
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"11" when e2,
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"00" when others;
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end architecture;
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