HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-A3PE3kL/top_synplify.npl

Add lpp_top_acq v0.0.1

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/ designs / ProjetBlanc-LeonLPP-A3PE3kL / top_synplify.npl

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				JDF G
				PROJECT top
				DESIGN top
				DEVFAM PROASIC3
				DEVICE A3PE3000L
				DEVSPEED Std
				DEVPKG ""
				DEVTOPLEVELMODULETYPE EDIF
				DEVSIMULATOR Modelsim
				DEVGENERATEDSIMULATIONMODEL VHDL
				SOURCE synplify\top.edf
				DEPASSOC top ..\..\boards\Projet-LeonLFR-A3P3K-Sheldon\top.ucf
				[Normal]
				xilxMapAllowLogicOpt=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
				xilxMapCoverMode=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Speed
				xilxNgdbld_AUL=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
				xilxPAReffortLevel=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Medium
				xilxNgdbldMacro=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1105378344, ..\..\netlists\xilinx\PROASIC3
				[STRATEGY-LIST]
				Normal=True

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