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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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-- 1.0 - initial version
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_lfr_ms_fsmdma IS
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PORT (
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-- AMBA AHB system signals
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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--TIME
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data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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-- fifo interface
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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-- header
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : IN STD_LOGIC;
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header_ack : OUT STD_LOGIC;
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-- DMA
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dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_valid : OUT STD_LOGIC;
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dma_valid_burst : OUT STD_LOGIC;
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dma_ren : IN STD_LOGIC;
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dma_done : IN STD_LOGIC;
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-- Reg out
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- Reg In
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status_ready_matrix_f0_0 : IN STD_LOGIC;
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status_ready_matrix_f0_1 : IN STD_LOGIC;
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status_ready_matrix_f1 : IN STD_LOGIC;
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status_ready_matrix_f2 : IN STD_LOGIC;
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status_error_anticipating_empty_fifo : IN STD_LOGIC;
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status_error_bad_component_error : IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
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matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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END;
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ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
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-----------------------------------------------------------------------------
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-- SIGNAL DMAIn : DMA_In_Type;
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-- SIGNAL header_dmai : DMA_In_Type;
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-- SIGNAL component_dmai : DMA_In_Type;
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-- SIGNAL DMAOut : DMA_OUt_Type;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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TYPE state_DMAWriteBurst IS (IDLE,
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CHECK_COMPONENT_TYPE,
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WRITE_COARSE_TIME,
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WRITE_FINE_TIME,
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TRASH_FIFO,
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SEND_DATA,
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WAIT_DATA_ACK
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);
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SIGNAL state : state_DMAWriteBurst; -- := IDLE;
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-- SIGNAL nbSend : INTEGER;
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SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL header_check_ok : STD_LOGIC;
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SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL send_matrix : STD_LOGIC;
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-- SIGNAL request : STD_LOGIC;
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-- SIGNAL remaining_data_request : INTEGER;
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SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL header_select : STD_LOGIC;
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SIGNAL header_send : STD_LOGIC;
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SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_send_ok : STD_LOGIC;
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SIGNAL header_send_ko : STD_LOGIC;
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SIGNAL component_send : STD_LOGIC;
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SIGNAL component_send_ok : STD_LOGIC;
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SIGNAL component_send_ko : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL fifo_ren_trash : STD_LOGIC;
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SIGNAL component_fifo_ren : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL log_empty_fifo : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_reg_val : STD_LOGIC;
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SIGNAL header_reg_ack : STD_LOGIC;
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SIGNAL header_error : STD_LOGIC;
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BEGIN
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debug_reg <= debug_reg_s;
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send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
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'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
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'1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
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'1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
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'0';
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header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
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'1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
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'1' WHEN component_type = component_type_pre + "0001" ELSE
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'0';
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address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
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addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
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addr_matrix_f1 WHEN matrix_type = "10" ELSE
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addr_matrix_f2 WHEN matrix_type = "11" ELSE
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(OTHERS => '0');
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-----------------------------------------------------------------------------
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-- DMA control
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-----------------------------------------------------------------------------
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DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
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BEGIN -- PROCESS DMAWriteBurst_p
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IF HRESETn = '0' THEN -- asynchronous reset (active low)
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matrix_type <= (OTHERS => '0');
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component_type <= (OTHERS => '0');
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state <= IDLE;
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-- header_ack <= '0';
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ready_matrix_f0_0 <= '0';
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ready_matrix_f0_1 <= '0';
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ready_matrix_f1 <= '0';
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ready_matrix_f2 <= '0';
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error_anticipating_empty_fifo <= '0';
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error_bad_component_error <= '0';
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component_type_pre <= "0000";
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fifo_ren_trash <= '1';
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component_send <= '0';
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address <= (OTHERS => '0');
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header_select <= '0';
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header_send <= '0';
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header_data <= (OTHERS => '0');
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fine_time_reg <= (OTHERS => '0');
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debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
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debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
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log_empty_fifo <= '0';
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ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
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debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
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header_reg_ack <= '0';
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CASE state IS
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WHEN IDLE =>
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debug_reg_s(2 DOWNTO 0) <= "000";
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--matrix_type <= header(1 DOWNTO 0);
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--component_type <= header(5 DOWNTO 2);
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ready_matrix_f0_0 <= '0';
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ready_matrix_f0_1 <= '0';
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ready_matrix_f1 <= '0';
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ready_matrix_f2 <= '0';
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error_bad_component_error <= '0';
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--header_select <= '1';
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IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
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header_reg_ack <= '1';
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debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0);
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debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2);
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matrix_type <= header_reg(1 DOWNTO 0);
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component_type <= header_reg(5 DOWNTO 2);
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component_type_pre <= component_type;
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state <= CHECK_COMPONENT_TYPE;
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END IF;
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log_empty_fifo <= '0';
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WHEN CHECK_COMPONENT_TYPE =>
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debug_reg_s(2 DOWNTO 0) <= "001";
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--header_ack <= '0';
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IF header_check_ok = '1' THEN
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header_send <= '0';
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--
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IF component_type = "0000" THEN
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address <= address_matrix;
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CASE matrix_type IS
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WHEN "00" => matrix_time_f0_0 <= data_time;
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WHEN "01" => matrix_time_f0_1 <= data_time;
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WHEN "10" => matrix_time_f1 <= data_time;
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WHEN "11" => matrix_time_f2 <= data_time;
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WHEN OTHERS => NULL;
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END CASE;
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header_data <= data_time(31 DOWNTO 0);
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fine_time_reg <= data_time(47 DOWNTO 32);
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--state <= WRITE_COARSE_TIME;
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--header_send <= '1';
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state <= SEND_DATA;
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header_send <= '0';
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component_send <= '1';
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header_select <= '0';
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ELSE
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state <= SEND_DATA;
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END IF;
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--
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ELSE
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error_bad_component_error <= '1';
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component_type_pre <= "0000";
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state <= TRASH_FIFO;
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END IF;
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--WHEN WRITE_COARSE_TIME =>
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-- debug_reg_s(2 DOWNTO 0) <= "010";
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-- header_ack <= '0';
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-- IF dma_ren = '0' THEN
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-- header_send <= '0';
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-- ELSE
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-- header_send <= header_send;
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-- END IF;
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-- IF header_send_ko = '1' THEN
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-- header_send <= '0';
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-- state <= TRASH_FIFO;
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-- error_anticipating_empty_fifo <= '1';
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-- -- TODO : error sending header
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-- ELSIF header_send_ok = '1' THEN
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-- header_send <= '1';
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-- header_select <= '1';
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-- header_data(15 DOWNTO 0) <= fine_time_reg;
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-- header_data(31 DOWNTO 16) <= (OTHERS => '0');
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-- state <= WRITE_FINE_TIME;
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-- address <= address + 4;
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-- END IF;
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--WHEN WRITE_FINE_TIME =>
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-- debug_reg_s(2 DOWNTO 0) <= "011";
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-- header_ack <= '0';
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-- IF dma_ren = '0' THEN
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-- header_send <= '0';
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-- ELSE
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-- header_send <= header_send;
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-- END IF;
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-- IF header_send_ko = '1' THEN
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-- header_send <= '0';
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-- state <= TRASH_FIFO;
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-- error_anticipating_empty_fifo <= '1';
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-- -- TODO : error sending header
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-- ELSIF header_send_ok = '1' THEN
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-- header_send <= '0';
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-- header_select <= '0';
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-- state <= SEND_DATA;
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-- address <= address + 4;
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-- END IF;
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WHEN TRASH_FIFO =>
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debug_reg_s(2 DOWNTO 0) <= "100";
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-- header_ack <= '0';
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error_bad_component_error <= '0';
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error_anticipating_empty_fifo <= '0';
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IF fifo_empty = '1' THEN
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state <= IDLE;
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fifo_ren_trash <= '1';
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ELSE
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fifo_ren_trash <= '0';
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END IF;
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WHEN SEND_DATA =>
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-- header_ack <= '0';
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debug_reg_s(2 DOWNTO 0) <= "101";
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IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
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state <= IDLE;
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IF component_type = "1110" THEN --"1110" -- JC
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CASE matrix_type IS
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WHEN "00" => ready_matrix_f0_0 <= '1';
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WHEN "01" => ready_matrix_f0_1 <= '1';
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WHEN "10" => ready_matrix_f1 <= '1';
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WHEN "11" => ready_matrix_f2 <= '1';
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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ELSE
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component_send <= '1';
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address <= address;
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state <= WAIT_DATA_ACK;
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END IF;
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WHEN WAIT_DATA_ACK =>
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log_empty_fifo <= fifo_empty OR log_empty_fifo;
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debug_reg_s(2 DOWNTO 0) <= "110";
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component_send <= '0';
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IF component_send_ok = '1' THEN
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address <= address + 64;
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state <= SEND_DATA;
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ELSIF component_send_ko = '1' THEN
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error_anticipating_empty_fifo <= '0';
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state <= TRASH_FIFO;
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END IF;
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--WHEN CHECK_LENGTH =>
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-- component_send <= '0';
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-- debug_reg_s(2 DOWNTO 0) <= "111";
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-- state <= IDLE;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS DMAWriteFSM_p;
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dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
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dma_valid <= header_send WHEN header_select = '1' ELSE '0';
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dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
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dma_addr <= address;
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fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
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component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
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component_send_ko <= '0';
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header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
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header_send_ko <= '0';
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-----------------------------------------------------------------------------
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-- FSM HEADER ACK
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-----------------------------------------------------------------------------
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PROCESS (HCLK, HRESETn)
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BEGIN -- PROCESS
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IF HRESETn = '0' THEN -- asynchronous reset (active low)
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header_ack <= '0';
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header_reg <= (OTHERS => '0');
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header_reg_val <= '0';
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ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
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header_ack <= '0';
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IF header_val = '1' THEN
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header_ack <= '1';
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header_reg <= header;
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END IF;
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IF header_val = '1' THEN
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header_reg_val <= '1';
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ELSIF header_reg_ack = '1' THEN
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header_reg_val <= '0';
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END IF;
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header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack);
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END IF;
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END PROCESS;
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debug_reg_s(3) <= header_error;
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END Behavioral;
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