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library ieee;
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use ieee.std_logic_1164.all;
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library grlib, techmap;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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-- pragma translate_off
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use gaisler.sim.all;
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library unisim;
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use unisim.ODDR2;
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-- pragma translate_on
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.general_purpose.all;
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use lpp.Rocket_PCM_Encoder.all;
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use work.Convertisseur_config.all;
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use work.config.all;
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entity ici4 is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
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);
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port (
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reset : in std_ulogic;
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clk : in std_ulogic;
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sclk : in std_logic;
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Gate : in std_logic;
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MinF : in std_logic;
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MajF : in std_logic;
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Data : out std_logic
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);
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end;
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architecture rtl of ici4 is
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signal clk_buf,reset_buf : std_logic;
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Constant FramePlacerCount : integer := 2;
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signal MinF_Inv : std_logic;
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signal Gate_Inv : std_logic;
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signal sclk_Inv : std_logic;
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signal WordCount : integer range 0 to WordCnt-1;
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signal WordClk : std_logic;
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signal data_int : std_logic;
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signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
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signal MuxIN : std_logic_vector((FramePlacerCount*WordSize)-1 downto 0);
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signal Sel : integer range 0 to 1;
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signal WORD0 : std_logic_vector(15 downto 0);
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signal WORD1 : std_logic_vector(15 downto 0);
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signal WORD2 : std_logic_vector(15 downto 0);
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signal WORD3 : std_logic_vector(15 downto 0);
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signal WORD4 : std_logic_vector(15 downto 0);
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signal WORD5 : std_logic_vector(15 downto 0);
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signal WORD6 : std_logic_vector(15 downto 0);
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signal WORD7 : std_logic_vector(15 downto 0);
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signal WORD8 : std_logic_vector(15 downto 0);
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signal WORD9 : std_logic_vector(15 downto 0);
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signal WORD10 : std_logic_vector(15 downto 0);
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signal WORD11 : std_logic_vector(15 downto 0);
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signal WORD12 : std_logic_vector(15 downto 0);
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signal LF1 : std_logic_vector(15 downto 0);
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signal LF2 : std_logic_vector(15 downto 0);
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signal LF3 : std_logic_vector(15 downto 0);
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signal MinFCnt : integer range 0 to MinFCount-1;
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signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
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begin
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clk_buf <= clk;
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reset_buf <= reset;
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--
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Gate_Inv <= not Gate;
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sclk_Inv <= not Sclk;
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MinF_Inv <= not MinF;
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data <= data_int;
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SD0 : Serial_Driver
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generic map(WordSize)
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port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
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WC0 : Word_Cntr
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generic map(WordSize,WordCnt)
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port map(sclk_Inv,MinF,WordClk,WordCount);
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MFC0 : MinF_Cntr
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generic map(MinFCount)
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port map(
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clk => MinF_Inv,
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reset => MajF,
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Cnt_out => MinFCnt
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);
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MUX0 : Serial_Driver_Multiplexor
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generic map(FramePlacerCount,WordSize)
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port map(sclk_Inv,Sel,MuxIN,MuxOUT);
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LFP0 : entity work.LF_FRAME_PLACER
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generic map(WordSize,WordCnt,MinFCount)
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port map(
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clk => Sclk,
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Wcount => WordCount,
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Flag => FramePlacerFlags(1),
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LF1 => LF1,
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LF2 => LF2,
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LF3 => LF3,
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WordOut => MuxIN(15 downto 8));
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CAMFP0 : entity work.ICI4_3DCAM_FRAM_PLACER
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generic map(WordSize,WordCnt,MinFCount)
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port map(
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clk => Sclk,
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Wcount => WordCount,
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Flag => FramePlacerFlags(0),
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WORD0 => WORD0,
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WORD1 => WORD1,
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WORD2 => WORD2,
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WORD3 => WORD3,
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WORD4 => WORD4,
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WORD5 => WORD5,
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WORD6 => WORD6,
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WORD7 => WORD7,
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WORD8 => WORD8,
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WORD9 => WORD9,
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WORD10 => WORD10,
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WORD11 => WORD11,
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WORD12 => WORD12,
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WordOut => MuxIN(7 downto 0));
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WORD0 <= WORD0cst;
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WORD1 <= WORD1cst;
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WORD2 <= WORD2cst;
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WORD3 <= WORD3cst;
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WORD4 <= WORD4cst;
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WORD5 <= WORD5cst;
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WORD6 <= WORD6cst;
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WORD7 <= WORD7cst;
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WORD8 <= WORD8cst;
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WORD9 <= WORD9cst;
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WORD10 <= WORD10cst;
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WORD11 <= WORD11cst;
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WORD12 <= X"0" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
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LF1 <= LF1cst;
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LF2 <= LF2cst;
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LF3 <= LF3cst;
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process(clk)
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variable SelVar : integer range 0 to FramePlacerCount;
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begin
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if clk'event and clk ='1' then
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Decoder: FOR i IN 0 to FramePlacerCount-1 loop
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if FramePlacerFlags(i) = '1' then
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SelVar := i;
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end if;
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END loop Decoder;
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Sel <= SelVar;
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end if;
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end process;
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end rtl;
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