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LFR-EQM 2.1.82 - b...
LFR-EQM 2.1.82 - b > SMP_CLK @ 24576MHz/25 = 983.03Hz > OEn active during one cycle > sample ADC_DATA one cycle after the OEn SMP_CLK --------|___________ CLK_25Mhz-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_| ADC_OEn ------------|___|----- ADC_DATA ****************{data} ADC_DATA_reg****************{data}
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r14:46dea010b1a4 default
r600:1d46c91bda8b simu_with_Leon3
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leon3mp.xcf
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NET clk_50mhz PERIOD = 20.000 ;
NET ddr_clk_fb PERIOD = 8.0 ns;
#TIMESPEC "TS_sepclk1" = FROM "clkgen0_clkin" TO "ddrsp0_ddr_phy0_clk" TIG;
#TIMESPEC "TS_sepclk2" = FROM "ddrsp0_ddr_phy0_clk" TO "clkgen0_clkin" TIG;
NET "clkm" TNM_NET = "clkm";
NET "clkml" TNM_NET = "clkml";
TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
NET "lock" TIG;