HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/beaglebone-test1/systest.c

LFR-EQM 2.1.82 - b...

LFR-EQM 2.1.82 - b > SMP_CLK @ 24576MHz/25 = 983.03Hz > OEn active during one cycle > sample ADC_DATA one cycle after the OEn SMP_CLK --------|___________ CLK_25Mhz-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_| ADC_OEn ------------|___|----- ADC_DATA ****************{data} ADC_DATA_reg****************{data}

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simu_with_Leon3

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             systest.c
        
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      main()

      {

      	report_start();

      //	svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);

      	base_test();

      /*

              greth_test(0x80000e00);

      	spw_test(0x80100A00);

      	spw_test(0x80100B00);

      	spw_test(0x80100C00);

      	svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);

      */

              report_end();

      }

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				main()

				{
				report_start();


				// svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
				base_test();
				/*
				greth_test(0x80000e00);
				spw_test(0x80100A00);
				spw_test(0x80100B00);
				spw_test(0x80100C00);
				svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0);
				*/
				report_end();
				}