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LFR-EQM 2.1.82 - b...
LFR-EQM 2.1.82 - b > SMP_CLK @ 24576MHz/25 = 983.03Hz > OEn active during one cycle > sample ADC_DATA one cycle after the OEn SMP_CLK --------|___________ CLK_25Mhz-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_| ADC_OEn ------------|___|----- ADC_DATA ****************{data} ADC_DATA_reg****************{data}
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readme.txt
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/ designs / Projet-LeonLFR-A3P3K-Sheldon_sim-all / CY7C1360C / readme.txt
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########################### READ ME #####################################
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****************************************************************************************************
Cypress Semiconductor
MPD Applications
VHDL Behavioral (Bus-functional) Model
---------------------------------------------------------------
Product Family: Std Sync Pipelined (SCD) Burst SRAM
Part: CY7C1360C
Density: 9M
Organization: 256K X 36
---------------------------------------------------------------
Rev: 1.0
Created: Aug 8th, 2005
Copyright(c) Cypress Semiconductor, 2004
All rights reserved
****************************************************************************************************
This is the VHDL model for the CY7C1360C device with the testbench and test vectors.
Contact "mpd_apps@cypress.com" if you have any questions.
This directory has 4 files, including this "readme".
FILE LIST:
----------
1) CY7C1360C.vhd -> Main File // VHDL model for CY7C1360C
2) SS_PL_SCD_X36_vect.txt -> Test Vectors File // used for testing the vhdl model
3) tb.vhd -> Test bench File // used for testing the vhdl model