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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: arith
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-- File: arith.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Description: Declaration of mul/div components
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package arith is
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type div32_in_type is record
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y : std_logic_vector(32 downto 0); -- Y (MSB divident)
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op1 : std_logic_vector(32 downto 0); -- operand 1 (LSB divident)
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op2 : std_logic_vector(32 downto 0); -- operand 2 (divisor)
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flush : std_logic;
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signed : std_logic;
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start : std_logic;
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end record;
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type div32_out_type is record
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ready : std_logic;
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nready : std_logic;
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icc : std_logic_vector(3 downto 0); -- ICC
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result : std_logic_vector(31 downto 0); -- div result
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end record;
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type mul32_in_type is record
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op1 : std_logic_vector(32 downto 0); -- operand 1
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op2 : std_logic_vector(32 downto 0); -- operand 2
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flush : std_logic;
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signed : std_logic;
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start : std_logic;
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mac : std_logic;
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acc : std_logic_vector(39 downto 0);
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--y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
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--asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
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end record;
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type mul32_out_type is record
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ready : std_logic;
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nready : std_logic;
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icc : std_logic_vector(3 downto 0); -- ICC
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result : std_logic_vector(63 downto 0); -- mul result
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end record;
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component div32
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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holdn : in std_ulogic;
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divi : in div32_in_type;
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divo : out div32_out_type
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);
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end component;
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component mul32
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generic (
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tech : integer := 0;
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multype : integer := 0;
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pipe : integer := 0;
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mac : integer := 0;
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arch : integer range 0 to 3 := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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holdn : in std_ulogic;
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muli : in mul32_in_type;
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mulo : out mul32_out_type
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);
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end component;
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function smult ( a, b : in std_logic_vector) return std_logic_vector;
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function umult ( a, b : in std_logic_vector) return std_logic_vector;
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end;
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package body arith is
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function smult ( a, b : in std_logic_vector) return std_logic_vector is
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variable sa : signed (a'length-1 downto 0);
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variable sb : signed (b'length-1 downto 0);
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variable sc : signed ((a'length + b'length) -1 downto 0);
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variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
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begin
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sa := signed(a); sb := signed(b);
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-- pragma translate_off
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if is_x(a) or is_x(b) then
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sc := (others => 'X');
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else
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-- pragma translate_on
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sc := sa * sb;
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-- pragma translate_off
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end if;
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-- pragma translate_on
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res := std_logic_vector(sc);
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return(res);
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end;
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function umult ( a, b : in std_logic_vector) return std_logic_vector is
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variable sa : unsigned (a'length-1 downto 0);
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variable sb : unsigned (b'length-1 downto 0);
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variable sc : unsigned ((a'length + b'length) -1 downto 0);
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variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
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begin
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sa := unsigned(a); sb := unsigned(b);
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-- pragma translate_off
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if is_x(a) or is_x(b) then
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sc := (others => 'X');
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else
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-- pragma translate_on
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sc := sa * sb;
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-- pragma translate_off
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end if;
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-- pragma translate_on
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res := std_logic_vector(sc);
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return(res);
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end;
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end;
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