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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@member.fsf.org
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity dynamic_freq_div is
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generic(
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PRESZ : integer range 1 to 32:=4;
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PREMAX : integer := 16#FFFFFF#;
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CPTSZ : integer range 1 to 32:=16
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);
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Port (
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clk : in STD_LOGIC;
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rstn : in STD_LOGIC;
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pre : in STD_LOGIC_VECTOR(PRESZ-1 downto 0);
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N : in STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
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Reload : in std_logic;
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clk_out : out STD_LOGIC
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);
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end dynamic_freq_div;
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architecture Behavioral of dynamic_freq_div is
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constant prescaller_reg_sz : integer := 2**PRESZ;
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constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1');
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signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');
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signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0');
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signal internal_clk : std_logic:='0';
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signal internal_clk_reg : std_logic:='0';
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signal clk_out_reg : std_logic:='0';
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begin
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max0: if (UNSIGNED(PREMAX_max) < PREMAX) generate
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internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=UNSIGNED(PREMAX_max)) else
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prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
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end generate;
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max1: if UNSIGNED(PREMAX_max) > PREMAX generate
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internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=PREMAX) else
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prescaller_reg(PREMAX);
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end generate;
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prescaller: process(rstn, clk)
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begin
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if rstn='0' then
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prescaller_reg <= (others => '0');
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elsif clk'event and clk = '1' then
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prescaller_reg <= std_logic_vector(UNSIGNED(prescaller_reg) + 1);
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end if;
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end process;
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clk_out <= clk_out_reg;
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counter: process(rstn, clk)
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begin
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if rstn='0' then
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cpt_reg <= (others => '0');
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internal_clk_reg <= '0';
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clk_out_reg <= '0';
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elsif clk'event and clk = '1' then
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internal_clk_reg <= internal_clk;
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if Reload = '1' then
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clk_out_reg <= '0';
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cpt_reg <= (others => '0');
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elsif (internal_clk = '1' and internal_clk_reg = '0') then
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if cpt_reg = N then
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clk_out_reg <= not clk_out_reg;
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cpt_reg <= (others => '0');
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else
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cpt_reg <= std_logic_vector(UNSIGNED(cpt_reg) + 1);
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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