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-- Convertisseur_config.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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Package Convertisseur_config is
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--===========================================================|
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--================== Variables Utiles =======================|
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--===========================================================|
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constant Fr�q_clk_Hz : integer := 27000000;
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constant D�bit_Hz : integer := 1000000;
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constant nb_compteur_sclk : integer := Fr�q_clk_Hz/D�bit_Hz;
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constant N_chanel : integer := 3;
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constant nb_mots : integer := 144;
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constant Vector_Dummy : std_logic_vector(23 downto 0) := X"FD1869";
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--===========================================================|
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--================= Configuration ADS =======================|
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--===========================================================|
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Type ADS_FORMAT_Type is array(2 downto 0) of std_logic;
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constant SPI_FORMAT : ADS_FORMAT_Type := "010";
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constant FSYNC_FORMAT : ADS_FORMAT_Type := "101";
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Type ADS_MODE_Type is array(1 downto 0) of std_logic;
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constant MODE_low_power : ADS_MODE_Type := "10";
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constant MODE_low_speed : ADS_MODE_Type := "11";
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constant MODE_high_resolution : ADS_MODE_Type := "01";
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Type ADS_config is
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record
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SYNC : std_logic;
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CLKDIV : std_logic;
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FORMAT : ADS_FORMAT_Type;
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MODE : ADS_MODE_Type;
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end record;
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--===========================================================|
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--================ Entr�es/Sorties ADS ======================|
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--=============== + init entr�es (simu) =====================|
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--===========================================================|
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Type Tbl_In is array(natural range <>) of std_logic;
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Type Tbl_Out is array(natural range <>) of std_logic_vector(23 downto 0);
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Type IN_ADS is
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record
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RDY : std_logic;
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Data_in : Tbl_In(1 to N_chanel);
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end record;
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Type OUT_ADS is
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record
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Vector_out : Tbl_Out(1 to N_chanel);
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end record;
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constant Data_inINIT : Tbl_In(1 to N_chanel) := (others => '0');
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constant IN_ADSINIT : IN_ADS := ('1',Data_inINIT);
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end;
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