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-- Convertisseur_Data.vhd
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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use work.Convertisseur_config.all;
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entity Convertisseur_Data is
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port(
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clk,raz : in std_logic;
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Minor_Frame : in std_logic;
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Compt_mots : in integer range 0 to nb_mots;
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HF_Data1,HF_Data2,HF_Data3 : in std_logic;
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LF_Data1,LF_Data2,LF_Data3 : in std_logic;
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sclk : out std_logic;
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ADS_HF_config : out ADS_config;
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ADS_LF_config : out ADS_config;
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Bit_fin_HF,Bit_fin_LF : out std_logic;
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Ready_HF,Ready_LF : out std_logic;
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ADS_LF_out : out OUT_ADS;
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HF_Vector1,HF_Vector2,HF_Vector3 : out std_logic_vector(15 downto 0));
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end Convertisseur_Data;
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architecture ar_Convertisseur_Data of Convertisseur_Data is
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signal ADS_HF_In : IN_ADS;
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signal ADS_LF_In : IN_ADS;
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signal unused : OUT_ADS;
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begin
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ADS_HF_In.Data_in(1) <= HF_Data1;
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ADS_HF_In.Data_in(2) <= HF_Data2;
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ADS_HF_In.Data_in(3) <= HF_Data3;
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ADS_LF_In.Data_in(1) <= LF_Data1;
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ADS_LF_In.Data_in(2) <= LF_Data2;
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ADS_LF_In.Data_in(3) <= LF_Data3;
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Ready_HF <= ADS_HF_In.RDY;
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Ready_LF <= ADS_LF_In.RDY;
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Frequence : entity work.Gene_Freq
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generic map (nb_mots)
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port map (clk,raz,Minor_Frame,Compt_mots,ADS_LF_In.RDY,ADS_HF_In.RDY);
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Donnees : entity work.Data
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port map (clk,raz,ADS_HF_In,ADS_LF_In,sclk,ADS_HF_config,ADS_LF_config,unused,ADS_LF_out,Bit_fin_HF,Bit_fin_LF,HF_Vector1,HF_Vector2,HF_Vector3);
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end ar_Convertisseur_Data;
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