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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.general_purpose.SYNC_FF;
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ENTITY top_ad_conv_RHF1401_withFilter IS
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GENERIC(
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ChanelCount : INTEGER := 8;
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ncycle_cnv_high : INTEGER := 25;
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ncycle_cnv : INTEGER := 50;
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FILTER_ENABLED : INTEGER := 16#FF#
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);
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PORT (
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cnv_clk : IN STD_LOGIC; -- 24Mhz
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cnv_rstn : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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clk : IN STD_LOGIC; -- 25MHz
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rstn : IN STD_LOGIC;
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ADC_data : IN Samples14;
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ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
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sample_val : OUT STD_LOGIC
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);
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END top_ad_conv_RHF1401_withFilter;
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ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
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SIGNAL cnv_cycle_counter : INTEGER;
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SIGNAL cnv_s : STD_LOGIC;
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SIGNAL cnv_s_reg : STD_LOGIC;
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SIGNAL cnv_sync : STD_LOGIC;
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SIGNAL cnv_sync_reg : STD_LOGIC;
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SIGNAL cnv_sync_falling : STD_LOGIC;
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SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
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SIGNAL enable_ADC : STD_LOGIC;
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SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
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SIGNAL channel_counter : INTEGER;
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CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
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SIGNAL ADC_data_selected : Samples14;
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SIGNAL ADC_data_result : Samples15;
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SIGNAL sample_counter : INTEGER;
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CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
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CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
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-----------------------------------------------------------------------------
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CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 2;
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CONSTANT DATA_CYCLE_VALID : INTEGER := 3;
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-- GEN OutPut Enable
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TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE);
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SIGNAL state_GEN_OEn : FSM_GEN_OEn_state;
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SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1;
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SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1;
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SIGNAL ADC_data_valid : STD_LOGIC;
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SIGNAL ADC_data_reg : Samples14;
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-----------------------------------------------------------------------------
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CONSTANT SAMPLE_DIVISION : INTEGER := 5;
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SIGNAL sample_val_s : STD_LOGIC;
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SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION;
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BEGIN
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-----------------------------------------------------------------------------
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-- CNV GEN
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-----------------------------------------------------------------------------
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PROCESS (cnv_clk, cnv_rstn)
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BEGIN -- PROCESS
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IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
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cnv_cycle_counter <= 0;
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cnv_s <= '0';
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ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
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IF cnv_cycle_counter < ncycle_cnv-1 THEN
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cnv_cycle_counter <= cnv_cycle_counter + 1;
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IF cnv_cycle_counter < ncycle_cnv_high-1 THEN
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cnv_s <= '1';
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ELSE
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cnv_s <= '0';
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END IF;
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ELSE
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cnv_s <= '1';
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cnv_cycle_counter <= 0;
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END IF;
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END IF;
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END PROCESS;
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cnv <= cnv_s;
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PROCESS (cnv_clk, cnv_rstn)
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BEGIN -- PROCESS
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IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
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cnv_s_reg <= '0';
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ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
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cnv_s_reg <= cnv_s;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- SYNC CNV
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-----------------------------------------------------------------------------
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SYNC_FF_cnv : SYNC_FF
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GENERIC MAP (
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NB_FF_OF_SYNC => 2)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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A => cnv_s_reg,
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A_sync => cnv_sync);
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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cnv_sync_reg <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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cnv_sync_reg <= cnv_sync;
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END IF;
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END PROCESS;
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cnv_sync_falling <= '1' WHEN cnv_sync = '0' AND cnv_sync_reg = '1' ELSE '0';
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-----------------------------------------------------------------------------
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-- GEN OutPut Enable
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN
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-------------------------------------------------------------------------
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ADC_nOE <= (OTHERS => '1');
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ADC_current <= 0;
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ADC_current_cycle_enabled <= 0;
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state_GEN_OEn <= IDLE;
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-------------------------------------------------------------------------
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ADC_data_reg <= (OTHERS => '0');
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all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP
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sample_reg(I) <= (OTHERS => '0');
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sample(I) <= (OTHERS => '0');
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END LOOP all_channel_sample_reg_init;
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sample_val <= '0';
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sample_val_s <= '0';
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sample_val_counter <= 0;
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-------------------------------------------------------------------------
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ELSIF clk'event AND clk = '1' THEN
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-------------------------------------------------------------------------
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sample_val_s <= '0';
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ADC_nOE <= (OTHERS => '1');
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CASE state_GEN_OEn IS
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WHEN IDLE =>
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IF cnv_sync_falling = '1' THEN
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ADC_nOE(0) <= '0';
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state_GEN_OEn <= GEN_OE;
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ADC_current <= 0;
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ADC_current_cycle_enabled <= 1;
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END IF;
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WHEN GEN_OE =>
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ADC_nOE(ADC_current) <= '0';
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ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1;
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IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN
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state_GEN_OEn <= WAIT_CYCLE;
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END IF;
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WHEN WAIT_CYCLE =>
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ADC_current_cycle_enabled <= 0;
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IF ADC_current = ChanelCount-1 THEN
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state_GEN_OEn <= IDLE;
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sample_val_s <= '1';
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ELSE
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ADC_current <= ADC_current + 1;
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state_GEN_OEn <= GEN_OE;
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END IF;
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WHEN OTHERS => NULL;
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END CASE;
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-------------------------------------------------------------------------
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ADC_data_reg <= ADC_data;
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all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP
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IF ADC_data_valid = '1' AND ADC_current = I THEN
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sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
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ELSE
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sample_reg(I) <= sample_reg(I);
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END IF;
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END LOOP all_channel_sample_reg;
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-------------------------------------------------------------------------
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sample_val <= '0';
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IF sample_val_s = '1' THEN
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IF sample_val_counter = SAMPLE_DIVISION-1 THEN
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sample_val_counter <= 0;
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sample_val <= '1'; -- TODO
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sample <= sample_reg;
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ELSE
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sample_val_counter <= sample_val_counter + 1;
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sample_val <= '0';
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END IF;
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END IF;
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END IF;
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END PROCESS;
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ADC_data_valid <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID ELSE '0';
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WITH ADC_current SELECT
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ADC_data_selected <= sample_reg(0) WHEN 0,
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sample_reg(1) WHEN 1,
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sample_reg(2) WHEN 2,
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sample_reg(3) WHEN 3,
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sample_reg(4) WHEN 4,
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sample_reg(5) WHEN 5,
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sample_reg(6) WHEN 6,
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sample_reg(7) WHEN 7,
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sample_reg(8) WHEN OTHERS ;
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ADC_data_result <= std_logic_vector((
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signed( ADC_data_selected(13) & ADC_data_selected) +
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signed( ADC_data_reg(13) & ADC_data_reg)
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));
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-- sample <= sample_reg;
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END ar_top_ad_conv_RHF1401;
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