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removed dependency to Xonsh for Validation LFR Filters

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lpp_delay.vhd
59 lines | 2.2 KiB | text/x-vhdl | VhdlLexer
------------------------------------------------------------------------------
-- This file is a part of the LPP VHDL IP LIBRARY
-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Author : Martin Morlot
-- Mail : martin.morlot@lpp.polytechnique.fr
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use std.textio.all;
library lpp;
use lpp.lpp_amba.all;
--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
package lpp_delay is
component APB_Delay is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
abits : integer := 8);
port (
clk : in std_logic; --! Horloge du composant
rst : in std_logic; --! Reset general du composant
apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
);
end component;
component TimerDelay is
port(
clk : in std_logic;
raz : in std_logic;
Start : in std_logic;
OKfin : in std_logic;
Fin : out std_logic;
Cpt : in std_logic_vector(25 downto 0)
);
end component;
end;