HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · lib/lpp/general_purpose/lpp_AMR/bclk_reg.vhd

removed dependency to Xonsh for Validation LFR Filters

martin - - Load All Authors

File last commit:

r80:b0b64ad7fab8 martin


                r648:0343834a1e0e

default

Download file

             bclk_reg.vhd
        
                    33 lines
            
             | 685 B
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / lib / lpp / general_purpose / lpp_AMR / bclk_reg.vhd
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      -- bclk_reg.vhd

      library IEEE;

      use IEEE.numeric_std.all;

      use IEEE.std_logic_1164.all;

      --! Simple bascule D utilise pour retarder d'un top d'horloge le signal d'entre

      entity bclk_reg is 

      port(

          clk,raz     : in std_logic;     --! Horloge 25Mhz et reset du systeme 

          D           : in std_logic;     --! Signal d'entre

          Q           : out std_logic);   --! Signal de sortie

      end bclk_reg;

      architecture ar_bclk_reg of bclk_reg is

      begin

          process(clk,raz)

              begin

              if(raz='0')then

                  Q <= '0';

              elsif(clk'event and clk='1')then

                 Q <= D;            

              end if;

          end process;

      end ar_bclk_reg;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

				-- bclk_reg.vhd
				library IEEE;
				use IEEE.numeric_std.all;
				use IEEE.std_logic_1164.all;

				--! Simple bascule D utilise pour retarder d'un top d'horloge le signal d'entre

				entity bclk_reg is

				port(
				clk,raz : in std_logic; --! Horloge 25Mhz et reset du systeme
				D : in std_logic; --! Signal d'entre
				Q : out std_logic); --! Signal de sortie

				end bclk_reg;


				architecture ar_bclk_reg of bclk_reg is

				begin
				process(clk,raz)
				begin

				if(raz='0')then
				Q <= '0';

				elsif(clk'event and clk='1')then
				Q <= D;

				end if;

				end process;

				end ar_bclk_reg;