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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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package amba_lcd_16x2_ctrlr is
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constant lcd_space_size : integer := 80;
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type FRM_Buff_Space is array(lcd_space_size-1 downto 0) of std_logic_vector(7 downto 0);
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type LCD_DRVR_CTRL_BUSS is
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record
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LCD_RW : std_logic;
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LCD_RS : std_logic;
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LCD_E : std_logic;
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LCD_DATA : std_logic_vector(7 downto 0);
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end record;
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type LCD_DRVR_SYNCH_BUSS is
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record
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DRVR_READY : std_logic;
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LCD_INITIALISED : std_logic;
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end record;
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type LCD_DRVR_CMD_BUSS is
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record
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Word : std_logic_vector(7 downto 0);
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CMD_Data : std_logic; --CMD = '0' and data = '1'
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Exec : std_logic;
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Duration : std_logic_vector(1 downto 0);
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end record;
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type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
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component LCD_16x2_DRIVER is
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generic(
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OSC_Freq_MHz : integer:=60
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);
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
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SYNCH : out LCD_DRVR_SYNCH_BUSS;
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DRIVER_CMD : in LCD_DRVR_CMD_BUSS
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);
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end component;
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component amba_lcd_16x2_driver is
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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Bp0 : in STD_LOGIC;
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Bp1 : in STD_LOGIC;
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Bp2 : in STD_LOGIC;
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LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
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LCD_RS : out STD_LOGIC;
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LCD_RW : out STD_LOGIC;
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LCD_E : out STD_LOGIC;
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LCD_RET : out STD_LOGIC;
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LCD_CS1 : out STD_LOGIC;
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LCD_CS2 : out STD_LOGIC;
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SF_CE0 : out std_logic
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);
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end component;
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component FRAME_CLK_GEN is
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generic(OSC_freqKHz : integer := 50000);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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FRAME_CLK : out STD_LOGIC);
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end component;
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component LCD_2x16_DRIVER is
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generic(
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OSC_Freq_MHz : integer:=60;
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Refresh_RateHz : integer:=5
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);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
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LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
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LCD_RS : out STD_LOGIC;
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LCD_RW : out STD_LOGIC;
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LCD_E : out STD_LOGIC;
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LCD_RET : out STD_LOGIC;
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LCD_CS1 : out STD_LOGIC;
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LCD_CS2 : out STD_LOGIC;
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STATEOUT: out std_logic_vector(3 downto 0);
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refreshPulse : out std_logic
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);
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end component;
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component LCD_CLK_GENERATOR is
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generic(OSC_freqKHz : integer := 50000);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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clk_1us : out STD_LOGIC);
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end component;
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component LCD_16x2_ENGINE is
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generic(OSC_freqKHz : integer := 50000);
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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DATA : in FRM_Buff_Space;
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CMD : in std_logic_vector(10 downto 0);
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Exec : in std_logic;
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Ready : out std_logic;
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LCD_CTRL : out LCD_DRVR_CTRL_BUSS
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);
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end component;
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component apb_lcd_ctrlr is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0;
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abits : integer := 8);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
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LCD_RS : out STD_LOGIC;
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LCD_RW : out STD_LOGIC;
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LCD_E : out STD_LOGIC;
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LCD_RET : out STD_LOGIC;
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LCD_CS1 : out STD_LOGIC;
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LCD_CS2 : out STD_LOGIC;
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SF_CE0 : out std_logic
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);
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end component;
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end;
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