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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lppFIFOxN IS
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GENERIC(
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tech : INTEGER := 0;
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Mem_use : INTEGER := use_RAM;
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Data_sz : INTEGER RANGE 1 TO 32 := 8;
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Addr_sz : INTEGER RANGE 2 TO 12 := 8;
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FifoCnt : INTEGER := 1
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);
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PORT(
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
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ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
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empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
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almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
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BEGIN
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fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
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lpp_fifo_1: lpp_fifo
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GENERIC MAP (
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tech => tech,
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Mem_use => Mem_use,
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DataSz => Data_sz,
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AddrSz => Addr_sz)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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reUse => reUse(I),
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ren => ren(I),
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rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
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wen => wen(I),
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wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
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empty => empty(I),
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full => full(I),
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almost_full => almost_full(I));
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END GENERATE;
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END ARCHITECTURE;
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