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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE std.textio.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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PACKAGE lpp_dma_pkg IS
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COMPONENT lpp_dma
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GENERIC (
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tech : INTEGER;
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hindex : INTEGER;
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pindex : INTEGER;
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paddr : INTEGER;
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pmask : INTEGER;
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pirq : INTEGER);
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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-- fifo interface
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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-- header
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : IN STD_LOGIC;
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header_ack : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT fifo_test_dma
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GENERIC (
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tech : INTEGER;
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pindex : INTEGER;
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paddr : INTEGER;
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pmask : INTEGER);
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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-- fifo interface
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fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : OUT STD_LOGIC;
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fifo_ren : IN STD_LOGIC;
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-- header
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header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : OUT STD_LOGIC;
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header_ack : IN STD_LOGIC
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);
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END COMPONENT;
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COMPONENT lpp_dma_apbreg
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GENERIC (
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pindex : INTEGER;
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paddr : INTEGER;
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pmask : INTEGER;
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pirq : INTEGER);
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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-- IN
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ready_matrix_f0_0 : IN STD_LOGIC;
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ready_matrix_f0_1 : IN STD_LOGIC;
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ready_matrix_f1 : IN STD_LOGIC;
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ready_matrix_f2 : IN STD_LOGIC;
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error_anticipating_empty_fifo : IN STD_LOGIC;
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error_bad_component_error : IN STD_LOGIC;
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debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- OUT
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status_ready_matrix_f0_0 : OUT STD_LOGIC;
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status_ready_matrix_f0_1 : OUT STD_LOGIC;
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status_ready_matrix_f1 : OUT STD_LOGIC;
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status_ready_matrix_f2 : OUT STD_LOGIC;
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status_error_anticipating_empty_fifo : OUT STD_LOGIC;
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status_error_bad_component_error : OUT STD_LOGIC;
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config_active_interruption_onNewMatrix : OUT STD_LOGIC;
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config_active_interruption_onError : OUT STD_LOGIC;
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addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT lpp_dma_send_1word
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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DMAIn : OUT DMA_In_Type;
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DMAOut : IN DMA_OUt_Type;
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send : IN STD_LOGIC;
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address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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send_ok : OUT STD_LOGIC;
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send_ko : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_dma_send_16word
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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DMAIn : OUT DMA_In_Type;
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DMAOut : IN DMA_OUt_Type;
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send : IN STD_LOGIC;
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address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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ren : OUT STD_LOGIC;
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send_ok : OUT STD_LOGIC;
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send_ko : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT fifo_latency_correction
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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dma_empty : OUT STD_LOGIC;
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dma_ren : IN STD_LOGIC);
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END COMPONENT;
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COMPONENT lpp_dma_ip
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GENERIC (
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tech : INTEGER;
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hindex : INTEGER);
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PORT (
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : IN STD_LOGIC;
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header_ack : OUT STD_LOGIC;
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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status_ready_matrix_f0_0 : IN STD_LOGIC;
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status_ready_matrix_f0_1 : IN STD_LOGIC;
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status_ready_matrix_f1 : IN STD_LOGIC;
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status_ready_matrix_f2 : IN STD_LOGIC;
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status_error_anticipating_empty_fifo : IN STD_LOGIC;
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status_error_bad_component_error : IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
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END COMPONENT;
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END;
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