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<?xml version="1.0" encoding="UTF-8" ?>
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<document>
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pn" timeStamp="Wed Dec 8 09:10:18 2010">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="314B616C181AFB6097A4EDCB224EA28B" type="project"/>
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<property name="ProjectIteration" value="11" type="project"/>
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<property name="ProjectFile" value="/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.xise" type="project"/>
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<property name="ProjectCreationTimestamp" value="2010-12-02T08:01:13" type="project"/>
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</section>
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<section name="Project Statistics" visible="true">
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<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
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<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
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<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
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<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
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<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
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<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
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<property name="PROP_SelectedInstanceHierarchicalPath" value="/APB_IIR_CEL/filter" type="process"/>
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<property name="PROP_Simulator" value="Modelsim-SE Mixed" type="design"/>
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<property name="PROP_SynthFsmEncode" value="None" type="process"/>
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<property name="PROP_SynthTopFile" value="changed" type="process"/>
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<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
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<property name="PROP_UseSmartGuide" value="false" type="design"/>
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<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
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<property name="PROP_intProjectCreationTimestamp" value="2010-12-02T08:01:13" type="design"/>
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<property name="PROP_intWbtProjectID" value="314B616C181AFB6097A4EDCB224EA28B" type="design"/>
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<property name="PROP_intWbtProjectIteration" value="11" type="process"/>
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<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
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<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
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<property name="PROP_map_otherCmdLineOptions" value="-timing" type="process"/>
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<property name="PROP_selectedSimRootSourceNode_behav" value="lpp.IIR_CEL_FILTER" type="process"/>
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<property name="PROP_xilxBitgCfg_GenOpt_DRC" value="false" type="process"/>
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<property name="PROP_xilxBitgCfg_GenOpt_ReadBack" value="true" type="process"/>
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<property name="PROP_xilxBitgStart_Clk_DriveDone" value="true" type="process"/>
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<property name="PROP_xilxMapPackRegInto" value="For Inputs and Outputs" type="process"/>
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<property name="PROP_xilxNgdbldMacro" value="changed" type="process"/>
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<property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
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<property name="PROP_xstBusDelimiter" value="()" type="process"/>
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<property name="PROP_xstPackIORegister" value="Yes" type="process"/>
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<property name="PROP_xst_otherCmdLineOptions" value="-uc leon3mp.xcf" type="process"/>
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<property name="PROP_AutoTop" value="false" type="design"/>
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<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
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<property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
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<property name="PROP_DevDevice" value="xc3s1600e" type="design"/>
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<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
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<property name="PROP_DevPackage" value="fg320" type="design"/>
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<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
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<property name="PROP_DevSpeed" value="-4" type="design"/>
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<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
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<property name="FILE_UCF" value="1" type="source"/>
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<property name="FILE_VHDL" value="302" type="source"/>
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</section>
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</application>
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</document>
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