##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Added cross domain synchronisation blocks.
Added cross domain synchronisation blocks.
jeandet - - Load All Authors

File last commit:

r129:8459a437c1f1 alexis
r223:006079fa8bed alexis
Show More
tb_Serial_Driver.vhd.bak
72 lines | 1.1 KiB | text/plain | TextLexer
/ designs / ICI4-Integ1 / ICI4HDL / tb_Serial_Driver.vhd.bak
History | Annotation | Raw |Copy content |Copy permalink
-- tb_Serial_Driver.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Serial_Driver is
end entity;
architecture ar_tb_Serial_Driver of tb_Serial_Driver is
constant Speed : integer := 4*1000*1000;
constant Tclk : time := real(1000*1000*1000/Speed) * 1 ns;
constant Size : integer := 8;
signal sclk : std_logic := '0';
signal inputDat : std_logic_vector(Size-1 downto 0);
signal load : std_logic:='0';
signal Gate : std_logic:='0';
signal Data : std_logic;
begin
SD0 : entity work.Serial_Driver
generic map(Size)
port map(
sclk,
inputDat,
load,
Gate,
Data
);
sclk <= not sclk after Tclk/2;
process
begin
inputDat <= std_logic_vector(TO_UNSIGNED(0,Size));
wait for 1ns;
load <= '1';
wait for 1ns;
load <= '0';
gate <= '1';
wait for Size * Tclk/2;
gate <= '0';
wait for 1ns;
inputDat <= std_logic_vector(TO_UNSIGNED(A5,Size));
wait for 1ns;
load <= '1';
wait for 1ns;
load <= '0';
gate <= '1';
wait for Size * Tclk/2;
gate <= '0';
wait for 1ns;
wait;
end process;
end ar_tb_Serial_Driver;