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-- Data.vhd
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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use work.Convertisseur_config.all;
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entity Data is
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port(
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clk,raz : in std_logic;
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ADS_HF_In : in IN_ADS;
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ADS_LF_In : in IN_ADS;
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sclk : out std_logic;
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ADS_HF_config : out ADS_config;
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ADS_LF_config : out ADS_config;
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ADS_HF_out : out OUT_ADS;
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ADS_LF_out : out OUT_ADS;
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Bit_fin_HF,Bit_fin_LF : out std_logic;
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Vector_HF1,Vector_HF2,Vector_HF3 : out std_logic_vector(15 downto 0));
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end Data;
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architecture ar_Data of Data is
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constant ADS_HF_c : ADS_config :=('1','1',FSYNC_FORMAT,MODE_low_power);
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constant ADS_LF_c : ADS_config :=('1','1',FSYNC_FORMAT,MODE_low_speed);
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signal Vect_1 : std_logic_vector(23 downto 0);
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signal Vect_2 : std_logic_vector(23 downto 0);
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signal Vect_3 : std_logic_vector(23 downto 0);
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signal sclk_int : std_logic;
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begin
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Clock_systeme : entity work.Sys_Clock
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generic map (nb_compteur_sclk)
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port map (clk,raz,sclk_int);
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Data_LF : entity work.Vectorize
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port map (clk,raz,sclk_int,ADS_LF_In.RDY,ADS_LF_In.Data_in(1),ADS_LF_In.Data_in(2),ADS_LF_In.Data_in(3),Bit_fin_LF,ADS_LF_out.Vector_out(1),ADS_LF_out.Vector_out(2),ADS_LF_out.Vector_out(3));
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Data_HF : entity work.Vectorize
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port map (clk,raz,sclk_int,ADS_HF_In.RDY,ADS_HF_In.Data_in(1),ADS_HF_In.Data_in(2),ADS_HF_In.Data_in(3),Bit_fin_HF,Vect_1,Vect_2,Vect_3);
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ADS_HF_config <= ADS_HF_c;
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ADS_LF_config <= ADS_LF_c;
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ADS_HF_out.Vector_out(1) <= Vect_1;
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ADS_HF_out.Vector_out(2) <= Vect_2;
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ADS_HF_out.Vector_out(3) <= Vect_3;
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Vector_HF1 <= Vect_1(23 downto 8);
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Vector_HF2 <= Vect_2(23 downto 8);
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Vector_HF3 <= Vect_3(23 downto 8);
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sclk <= sclk_int;
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end ar_Data;
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