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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.AMBA_TestPackage.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.libdcom.ALL;
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USE gaisler.sim.ALL;
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USE gaisler.jtagtst.ALL;
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USE gaisler.misc.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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LIBRARY lpp;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.testbench_package.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.CY7C1061DV33_pkg.ALL;
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ENTITY tb_memory IS
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GENERIC (
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n_ahb_m : INTEGER := 2;
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n_ahb_s : INTEGER := 1);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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ahbsi : OUT ahb_slv_in_type;
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ahbso : IN ahb_slv_out_vector := (OTHERS => ahbs_none);
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ahbmi : OUT ahb_mst_in_type;
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ahbmo : IN ahb_mst_out_vector := (OTHERS => ahbm_none)
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);
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END tb_memory;
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ARCHITECTURE beh OF tb_memory IS
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-----------------------------------------------------------------------------
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SIGNAL memi : memory_in_type;
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SIGNAL memo : memory_out_type;
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SIGNAL wpo : wprot_out_type;
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SIGNAL sdo : sdram_out_type;
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-----------------------------------------------------------------------------
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SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
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SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL nSRAM_BE0 : STD_LOGIC;
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SIGNAL nSRAM_BE1 : STD_LOGIC;
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SIGNAL nSRAM_BE2 : STD_LOGIC;
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SIGNAL nSRAM_BE3 : STD_LOGIC;
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SIGNAL nSRAM_WE : STD_LOGIC;
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SIGNAL nSRAM_CE : STD_LOGIC;
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SIGNAL nSRAM_OE : STD_LOGIC;
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-----------------------------------------------------------------------------
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BEGIN -- beh
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ahb0 : ahbctrl
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GENERIC MAP (
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defmast => 0,
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split => 0,
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rrobin => 1,
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ioaddr => 16#FFF#,
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ioen => 0,
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nahbm => n_ahb_s,
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nahbs => n_ahb_m)
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PORT MAP (
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rstn,
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clk,
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ahbmi,
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ahbmo,
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ahbsi,
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ahbso);
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memi.brdyn <= '1';
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memi.bexcn <= '1';
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memi.writen <= '1';
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memi.wrn <= "1111";
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memi.bwidth <= "10";
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bdr : FOR i IN 0 TO 3 GENERATE
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data_pad : iopadv GENERIC MAP (tech => inferred, width => 8)
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PORT MAP (
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data(31-i*8 DOWNTO 24-i*8),
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memo.data(31-i*8 DOWNTO 24-i*8),
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memo.bdrive(i),
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memi.data(31-i*8 DOWNTO 24-i*8));
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END GENERATE;
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address <= memo.address(21 DOWNTO 2);
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nSRAM_CE <= NOT(memo.ramsn(0));
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nSRAM_OE <= memo.ramoen(0);
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nSRAM_WE <= memo.writen;
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nSRAM_BE0 <= memo.mben(3);
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nSRAM_BE1 <= memo.mben(2);
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nSRAM_BE2 <= memo.mben(1);
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nSRAM_BE3 <= memo.mben(0);
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async_1Mx16_0: CY7C1061DV33
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GENERIC MAP (
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ADDR_BITS => 20,
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DATA_BITS => 16,
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depth => 1048576,
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MEM_ARRAY_DEBUG => 32,
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TimingInfo => TRUE,
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TimingChecks => '1')
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PORT MAP (
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CE1_b => '0',
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CE2 => nSRAM_CE,
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WE_b => nSRAM_WE,
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OE_b => nSRAM_OE,
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BHE_b => nSRAM_BE1,
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BLE_b => nSRAM_BE0,
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A => address,
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DQ => data(15 DOWNTO 0));
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async_1Mx16_1: CY7C1061DV33
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GENERIC MAP (
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ADDR_BITS => 20,
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DATA_BITS => 16,
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depth => 1048576,
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MEM_ARRAY_DEBUG => 32,
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TimingInfo => TRUE,
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TimingChecks => '1')
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PORT MAP (
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CE1_b => '0',
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CE2 => nSRAM_CE,
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WE_b => nSRAM_WE,
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OE_b => nSRAM_OE,
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BHE_b => nSRAM_BE3,
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BLE_b => nSRAM_BE2,
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A => address,
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DQ => data(31 DOWNTO 16));
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END beh;
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