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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.AMBA_TestPackage.ALL;
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LIBRARY gaisler;
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USE gaisler.memctrl.ALL;
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USE gaisler.leon3.ALL;
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USE gaisler.uart.ALL;
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USE gaisler.misc.ALL;
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USE gaisler.libdcom.ALL;
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USE gaisler.sim.ALL;
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USE gaisler.jtagtst.ALL;
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USE gaisler.misc.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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LIBRARY esa;
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USE esa.memoryctrl.ALL;
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LIBRARY lpp;
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USE lpp.lpp_waveform_pkg.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_ad_conv.ALL;
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USE lpp.testbench_package.ALL;
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USE lpp.lpp_lfr_pkg.ALL;
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USE lpp.iir_filter.ALL;
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USE lpp.general_purpose.ALL;
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USE lpp.CY7C1061DV33_pkg.ALL;
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USE lpp.FILTERcfg.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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USE lpp.lpp_top_lfr_pkg.ALL;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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SIGNAL apbi : apb_slv_in_type;
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SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
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SIGNAL ahbsi : ahb_slv_in_type;
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SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
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SIGNAL ahbmi : ahb_mst_in_type;
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SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- DMA
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-----------------------------------------------------------------------------
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SIGNAL dma_send : STD_LOGIC;
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SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
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SIGNAL dma_done : STD_LOGIC;
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SIGNAL dma_ren : STD_LOGIC;
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SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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-- WFP
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-----------------------------------------------------------------------------
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SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f0_data_out_valid : STD_LOGIC := '0';
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SIGNAL data_f0_data_out_valid_burst : STD_LOGIC := '0';
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SIGNAL data_f0_data_out_ren : STD_LOGIC;
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SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f1_data_out_valid : STD_LOGIC := '0';
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SIGNAL data_f1_data_out_valid_burst : STD_LOGIC := '0';
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SIGNAL data_f1_data_out_ren : STD_LOGIC;
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SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f2_data_out_valid : STD_LOGIC := '0';
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SIGNAL data_f2_data_out_valid_burst : STD_LOGIC := '0';
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SIGNAL data_f2_data_out_ren : STD_LOGIC;
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SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_f3_data_out_valid : STD_LOGIC := '0';
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SIGNAL data_f3_data_out_valid_burst : STD_LOGIC := '0';
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SIGNAL data_f3_data_out_ren : STD_LOGIC;
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-----------------------------------------------------------------------------
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-- ARBITER
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-----------------------------------------------------------------------------
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SIGNAL dma_sel_valid : STD_LOGIC;
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SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- MS
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-----------------------------------------------------------------------------
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SIGNAL ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL ready_matrix_f1 : STD_LOGIC;
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SIGNAL ready_matrix_f2 : STD_LOGIC;
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SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL error_bad_component_error : STD_LOGIC;
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SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f2 : STD_LOGIC;
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SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL status_error_bad_component_error : STD_LOGIC;
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SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
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SIGNAL config_active_interruption_onError : STD_LOGIC;
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SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
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--
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SIGNAL sample_f0_val : STD_LOGIC;
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SIGNAL sample_f1_val : STD_LOGIC;
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SIGNAL sample_f3_val : STD_LOGIC;
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--
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SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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--
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SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_ms_valid : STD_LOGIC;
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SIGNAL data_ms_valid_burst : STD_LOGIC;
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SIGNAL data_ms_ren : STD_LOGIC;
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SIGNAL data_ms_done : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
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SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL run : STD_LOGIC := '1';
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-----------------------------------------------------------------------------
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SIGNAL dma_counter : INTEGER;
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SIGNAL dma_done_reg : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL sample_counter_24k : INTEGER;
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SIGNAL s_24576Hz : STD_LOGIC;
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SIGNAL clk49_152MHz : STD_LOGIC := '0';
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SIGNAL s_24_sync_reg_0 : STD_LOGIC;
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SIGNAL s_24_sync_reg_1 : STD_LOGIC;
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SIGNAL s_24576Hz_sync : STD_LOGIC;
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SIGNAL sample_counter_f1 : INTEGER;
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SIGNAL sample_counter_f2 : INTEGER;
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-----------------------------------------------------------------------------
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BEGIN
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-----------------------------------------------------------------------------
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clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
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clk <= NOT clk AFTER 5 ns; -- 100 MHz
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rstn <= '1' AFTER 30 ns;
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-----------------------------------------------------------------------------
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PROCESS (clk49_152MHz, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_counter_24k <= 0;
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s_24576Hz <= '0';
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ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
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IF sample_counter_24k = 0 THEN
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sample_counter_24k <= 2000;
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s_24576Hz <= NOT s_24576Hz;
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ELSE
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sample_counter_24k <= sample_counter_24k - 1;
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END IF;
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END IF;
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END PROCESS;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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s_24_sync_reg_0 <= '0';
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s_24_sync_reg_1 <= '0';
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s_24576Hz_sync <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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s_24_sync_reg_0 <= s_24576Hz;
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s_24_sync_reg_1 <= s_24_sync_reg_0;
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s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
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END IF;
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END PROCESS;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_f0_val <= '0';
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sample_f1_val <= '0';
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sample_f3_val <= '0';
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sample_counter_f1 <= 0;
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sample_counter_f2 <= 0;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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IF s_24576Hz_sync = '1' THEN
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sample_f0_val <= '1';
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IF sample_counter_f1 = 0 THEN
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sample_f1_val <= '1';
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sample_counter_f1 <= 5;
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ELSE
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sample_f1_val <= '0';
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sample_counter_f1 <= sample_counter_f1 -1;
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END IF;
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IF sample_counter_f2 = 0 THEN
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sample_f3_val <= '1';
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sample_counter_f2 <= 95;
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ELSE
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sample_f3_val <= '0';
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sample_counter_f2 <= sample_counter_f2 -1;
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END IF;
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ELSE
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sample_f0_val <= '0';
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sample_f1_val <= '0';
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sample_f3_val <= '0';
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END IF;
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END IF;
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END PROCESS;
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sample_f0_data <= (OTHERS => '0');
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sample_f1_data <= (OTHERS => '0');
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sample_f3_data <= (OTHERS => '0');
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-----------------------------------------------------------------------------
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sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
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sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
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sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val);
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-- (MSB) E2 E1 B2 B1 B0 (LSB)
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sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));
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sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
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sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
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-----------------------------------------------------------------------------
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tb: PROCESS
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BEGIN
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WAIT UNTIL rstn = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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status_ready_matrix_f0_0 <= '0';
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status_ready_matrix_f0_1 <= '0';
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status_ready_matrix_f1 <= '0';
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status_ready_matrix_f2 <= '0';
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status_error_anticipating_empty_fifo <= '0';
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status_error_bad_component_error <= '0';
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config_active_interruption_onNewMatrix <= '1';
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config_active_interruption_onError <= '0';
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addr_matrix_f0_0 <= X"40000000";
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addr_matrix_f0_1 <= X"40020000";
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addr_matrix_f1 <= X"40040000";
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addr_matrix_f2 <= X"40060000";
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WAIT UNTIL clk = '1';
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END PROCESS tb;
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-----------------------------------------------------------------------------
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-- MS
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-----------------------------------------------------------------------------
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lpp_lfr_ms_1 : lpp_lfr_ms
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GENERIC MAP (
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Mem_use => use_RAM)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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coarse_time => coarse_time,
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fine_time => fine_time,
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sample_f0_wen => sample_f0_wen,
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sample_f0_wdata => sample_f0_wdata,
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sample_f1_wen => sample_f1_wen,
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sample_f1_wdata => sample_f1_wdata,
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sample_f3_wen => sample_f3_wen,
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sample_f3_wdata => sample_f3_wdata,
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dma_addr => data_ms_addr, --
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dma_data => data_ms_data, --
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dma_valid => data_ms_valid, --
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dma_valid_burst => data_ms_valid_burst, --
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dma_ren => data_ms_ren, --
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dma_done => data_ms_done, --
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-- reg out
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ready_matrix_f0_0 => ready_matrix_f0_0,
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ready_matrix_f0_1 => ready_matrix_f0_1,
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ready_matrix_f1 => ready_matrix_f1,
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ready_matrix_f2 => ready_matrix_f2,
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error_anticipating_empty_fifo => error_anticipating_empty_fifo,
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error_bad_component_error => error_bad_component_error,
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debug_reg => observation_reg, --debug_reg,
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-- reg in
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status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
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status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
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status_ready_matrix_f1 => status_ready_matrix_f1,
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status_ready_matrix_f2 => status_ready_matrix_f2,
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status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
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status_error_bad_component_error => status_error_bad_component_error,
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config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
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config_active_interruption_onError => config_active_interruption_onError,
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addr_matrix_f0_0 => addr_matrix_f0_0,
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addr_matrix_f0_1 => addr_matrix_f0_1,
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addr_matrix_f1 => addr_matrix_f1,
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addr_matrix_f2 => addr_matrix_f2,
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matrix_time_f0_0 => matrix_time_f0_0,
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matrix_time_f0_1 => matrix_time_f0_1,
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matrix_time_f1 => matrix_time_f1,
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matrix_time_f2 => matrix_time_f2);
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-----------------------------------------------------------------------------
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-- ARBITER
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-----------------------------------------------------------------------------
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|
|
dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
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|
dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
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dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
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dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
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|
RR_Arbiter_4_1 : RR_Arbiter_4
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
in_valid => dma_rr_valid,
|
|
|
out_grant => dma_rr_grant_s);
|
|
|
|
|
|
dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
|
|
|
dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
|
|
|
dma_rr_valid_ms(2) <= '0';
|
|
|
dma_rr_valid_ms(3) <= '0';
|
|
|
|
|
|
RR_Arbiter_4_2 : RR_Arbiter_4
|
|
|
PORT MAP (
|
|
|
clk => clk,
|
|
|
rstn => rstn,
|
|
|
in_valid => dma_rr_valid_ms,
|
|
|
out_grant => dma_rr_grant_ms);
|
|
|
|
|
|
dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
|
|
|
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN -- PROCESS
|
|
|
IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
dma_sel <= (OTHERS => '0');
|
|
|
dma_send <= '0';
|
|
|
dma_valid_burst <= '0';
|
|
|
data_ms_done <= '0';
|
|
|
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
|
|
|
IF run = '1' THEN
|
|
|
data_ms_done <= '0';
|
|
|
IF dma_sel = "00000" OR dma_done = '1' THEN
|
|
|
dma_sel <= dma_rr_grant;
|
|
|
IF dma_rr_grant(0) = '1' THEN
|
|
|
dma_send <= '1';
|
|
|
dma_valid_burst <= data_f0_data_out_valid_burst;
|
|
|
dma_sel_valid <= data_f0_data_out_valid;
|
|
|
ELSIF dma_rr_grant(1) = '1' THEN
|
|
|
dma_send <= '1';
|
|
|
dma_valid_burst <= data_f1_data_out_valid_burst;
|
|
|
dma_sel_valid <= data_f1_data_out_valid;
|
|
|
ELSIF dma_rr_grant(2) = '1' THEN
|
|
|
dma_send <= '1';
|
|
|
dma_valid_burst <= data_f2_data_out_valid_burst;
|
|
|
dma_sel_valid <= data_f2_data_out_valid;
|
|
|
ELSIF dma_rr_grant(3) = '1' THEN
|
|
|
dma_send <= '1';
|
|
|
dma_valid_burst <= data_f3_data_out_valid_burst;
|
|
|
dma_sel_valid <= data_f3_data_out_valid;
|
|
|
ELSIF dma_rr_grant(4) = '1' THEN
|
|
|
dma_send <= '1';
|
|
|
dma_valid_burst <= data_ms_valid_burst;
|
|
|
dma_sel_valid <= data_ms_valid;
|
|
|
END IF;
|
|
|
|
|
|
IF dma_sel(4) = '1' THEN
|
|
|
data_ms_done <= '1';
|
|
|
END IF;
|
|
|
ELSE
|
|
|
dma_sel <= dma_sel;
|
|
|
dma_send <= '0';
|
|
|
END IF;
|
|
|
ELSE
|
|
|
data_ms_done <= '0';
|
|
|
dma_sel <= (OTHERS => '0');
|
|
|
dma_send <= '0';
|
|
|
dma_valid_burst <= '0';
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
|
|
|
dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
|
|
|
data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
|
|
|
data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
|
|
|
data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
|
|
|
data_ms_addr;
|
|
|
|
|
|
dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
|
|
|
data_f1_data_out WHEN dma_sel(1) = '1' ELSE
|
|
|
data_f2_data_out WHEN dma_sel(2) = '1' ELSE
|
|
|
data_f3_data_out WHEN dma_sel(3) = '1' ELSE
|
|
|
data_ms_data;
|
|
|
|
|
|
data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
|
|
|
data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
|
|
|
data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
|
|
|
data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
|
|
|
data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- DMA
|
|
|
-----------------------------------------------------------------------------
|
|
|
--lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
|
|
|
-- GENERIC MAP (
|
|
|
-- tech => inferred,
|
|
|
-- hindex => 0)
|
|
|
-- PORT MAP (
|
|
|
-- HCLK => clk,
|
|
|
-- HRESETn => rstn,
|
|
|
-- run => run,
|
|
|
-- AHB_Master_In => ahbmi,
|
|
|
-- AHB_Master_Out => ahbmo(0),
|
|
|
|
|
|
-- send => dma_send,
|
|
|
-- valid_burst => dma_valid_burst,
|
|
|
-- done => dma_done,
|
|
|
-- ren => dma_ren,
|
|
|
-- address => dma_address,
|
|
|
-- data => dma_data);
|
|
|
|
|
|
PROCESS (clk, rstn)
|
|
|
BEGIN -- PROCESS
|
|
|
IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
dma_counter <= 0;
|
|
|
dma_done_reg <= '0';
|
|
|
dma_done <= '0';
|
|
|
dma_ren <= '1';
|
|
|
ELSIF clk'event AND clk = '1' THEN -- rising clock edge
|
|
|
dma_done_reg <= '0';
|
|
|
dma_ren <= '1';
|
|
|
|
|
|
IF dma_send = '1' THEN
|
|
|
dma_counter <= 15;
|
|
|
dma_done_reg <= '0';
|
|
|
dma_ren <= '0';
|
|
|
END IF;
|
|
|
|
|
|
IF dma_counter > 0 THEN
|
|
|
IF dma_counter = 1 THEN
|
|
|
dma_done_reg <= '1';
|
|
|
END IF;
|
|
|
dma_ren <= '0';
|
|
|
dma_counter <= dma_counter - 1;
|
|
|
END IF;
|
|
|
|
|
|
dma_done <= dma_done_reg;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
-- MEMORY + AHB CTRL
|
|
|
-----------------------------------------------------------------------------
|
|
|
--tb_memory_1: tb_memory
|
|
|
-- GENERIC MAP (
|
|
|
-- n_ahb_m => 2,
|
|
|
-- n_ahb_s => 1)
|
|
|
-- PORT MAP (
|
|
|
-- clk => clk,
|
|
|
-- rstn => rstn,
|
|
|
-- ahbsi => ahbsi,
|
|
|
-- ahbso => ahbso,
|
|
|
-- ahbmi => ahbmi,
|
|
|
-- ahbmo => ahbmo);
|
|
|
-----------------------------------------------------------------------------
|
|
|
END;
|
|
|
|
