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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: alltap
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-- File: alltap.vhd
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-- Author: Edvin Catovic - Gaisler Research
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-- Description: JTAG Test Access Port (TAP) Controller component declaration
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package alltap is
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component tap_gen
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generic (
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irlen : integer range 2 to 8 := 2;
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idcode : integer range 0 to 255 := 9;
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manf : integer range 0 to 2047 := 804;
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part : integer range 0 to 65535 := 0;
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ver : integer range 0 to 15 := 0;
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trsten : integer range 0 to 1 := 1;
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scantest : integer := 0);
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port (
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trst : in std_ulogic;
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tckp : in std_ulogic;
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tckn : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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tapi_en1 : in std_ulogic;
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_inst : out std_logic_vector(7 downto 0);
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic;
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testen : in std_ulogic := '0';
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testrst : in std_ulogic := '1';
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tdoen : out std_ulogic
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);
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end component;
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component virtex_tap
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port (
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic
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);
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end component;
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component virtex2_tap
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port (
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic
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);
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end component;
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component virtex4_tap
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port (
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic
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);
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end component;
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component virtex5_tap
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port (
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic
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);
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end component;
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component spartan3_tap
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port (
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic
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);
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end component;
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component altera_tap
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port (
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_inst : out std_logic_vector(7 downto 0);
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic
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);
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end component;
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component fusion_tap
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port (
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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trst : in std_ulogic;
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tdo : out std_ulogic;
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapi_en1 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_inst : out std_logic_vector(7 downto 0)
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);
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end component;
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component proasic3_tap
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port (
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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trst : in std_ulogic;
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tdo : out std_ulogic;
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapi_en1 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_inst : out std_logic_vector(7 downto 0)
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);
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end component;
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component proasic3e_tap
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port (
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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trst : in std_ulogic;
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tdo : out std_ulogic;
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapi_en1 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_inst : out std_logic_vector(7 downto 0)
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);
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end component;
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component proasic3l_tap
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port (
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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trst : in std_ulogic;
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tdo : out std_ulogic;
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapi_en1 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_inst : out std_logic_vector(7 downto 0)
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);
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end component;
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component virtex6_tap
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port (
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic
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);
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end component;
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component spartan6_tap
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port (
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tapi_tdo1 : in std_ulogic;
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tapi_tdo2 : in std_ulogic;
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tapo_tck : out std_ulogic;
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tapo_tdi : out std_ulogic;
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tapo_rst : out std_ulogic;
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tapo_capt : out std_ulogic;
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tapo_shft : out std_ulogic;
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tapo_upd : out std_ulogic;
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tapo_xsel1 : out std_ulogic;
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tapo_xsel2 : out std_ulogic
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);
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end component;
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-------------------------------------------------------------------------------
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component scanregi_inf
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port (
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pad : in std_ulogic;
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core : out std_ulogic;
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tck : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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bsshft : in std_ulogic;
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bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
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bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
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bsdrive : in std_ulogic; -- drive data reg to core
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bshighz : in std_ulogic
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);
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end component;
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component scanrego_inf
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port (
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pad : out std_ulogic;
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core : in std_ulogic;
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samp : in std_ulogic; -- normally same as core unless outpad has feedback
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tck : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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bsshft : in std_ulogic;
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bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
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bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
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bsdrive : in std_ulogic -- drive data reg to pad
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);
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end component;
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component scanregio_inf -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
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generic (
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hzsup : integer range 0 to 1 := 1
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);
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port (
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pado : out std_ulogic;
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padoen : out std_ulogic;
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padi : in std_ulogic;
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coreo : in std_ulogic;
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coreoen : in std_ulogic;
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corei : out std_ulogic;
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tck : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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bsshft : in std_ulogic;
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bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
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bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
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bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
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bsdrive : in std_ulogic; -- drive outdata regs to pad,
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-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
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bshighz : in std_ulogic
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);
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end component;
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end;
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