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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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library esa;
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use esa.memoryctrl.all;
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use work.config.all;
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library lpp;
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use lpp.lpp_amba.all;
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use lpp.lpp_memory.all;
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use lpp.lpp_uart.all;
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use lpp.lpp_matrix.all;
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use lpp.lpp_delay.all;
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use lpp.lpp_fft.all;
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use lpp.fft_components.all;
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use lpp.lpp_ad_conv.all;
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use lpp.iir_filter.all;
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use lpp.general_purpose.all;
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use lpp.Filtercfg.all;
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use lpp.lpp_cna.all;
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use lpp.lpp_demux.all;
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use lpp.lpp_Header.all;
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use lpp.lpp_dma_pkg.all;
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use lpp.lpp_top_lfr_pkg.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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clk50MHz : in std_ulogic;
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reset : in std_ulogic;
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ramclk : out std_logic;
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ahbrxd : in std_ulogic; -- DSU rx data
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ahbtxd : out std_ulogic; -- DSU tx data
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dsubre : in std_ulogic;
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dsuact : out std_ulogic;
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urxd1 : in std_ulogic; -- UART1 rx data
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utxd1 : out std_ulogic; -- UART1 tx data
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errorn : out std_ulogic;
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address : out std_logic_vector(18 downto 0);
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data : inout std_logic_vector(31 downto 0);
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gpio : inout std_logic_vector(6 downto 0); -- I/O port
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nBWa : out std_logic;
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nBWb : out std_logic;
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nBWc : out std_logic;
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nBWd : out std_logic;
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nBWE : out std_logic;
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nADSC : out std_logic;
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nADSP : out std_logic;
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nADV : out std_logic;
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nGW : out std_logic;
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nCE1 : out std_logic;
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CE2 : out std_logic;
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nCE3 : out std_logic;
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nOE : out std_logic;
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MODE : out std_logic;
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SSRAM_CLK : out std_logic;
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ZZ : out std_logic;
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---------------------------------------------------------------------
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--- AJOUT TEST ------------------------In/Out-----------------------
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---------------------------------------------------------------------
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-- ACQ
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CNV_CH1 : OUT STD_LOGIC;
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SCK_CH1 : OUT STD_LOGIC;
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SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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Bias_Fails : out std_logic;
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-- DAC
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DAC_EN : out std_logic;
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DAC_SYNC : out std_logic;
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DAC_SCLK : out std_logic;
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DAC_DATA : out std_logic;
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-- UART
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UART_RXD : in std_logic;
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UART_TXD : out std_logic;
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-- DEBUG
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SPW1_EN : out std_logic;
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SPW2_EN : out std_logic;
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testspw1S : out std_logic;
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testspw1D : out std_logic;
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testled0 : out std_logic;
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testled1 : out std_logic;
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---------------------------------------------------------------------
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led : out std_logic_vector(1 downto 0)
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);
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end;
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architecture Behavioral of leon3mp is
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constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
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CFG_GRETH+CFG_AHB_JTAG;
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constant maxahbm : integer := maxahbmsp;
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--Clk & Rst g�n�
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signal vcc : std_logic_vector(4 downto 0);
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signal gnd : std_logic_vector(4 downto 0);
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signal resetnl : std_ulogic;
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signal clk2x : std_ulogic;
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signal lclk : std_ulogic;
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signal lclk2x : std_ulogic;
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signal clkm : std_ulogic;
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signal rstn : std_ulogic;
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signal rstraw : std_ulogic;
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signal pciclk : std_ulogic;
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signal sdclkl : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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--- AHB / APB
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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--UART
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signal ahbuarti : uart_in_type;
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signal ahbuarto : uart_out_type;
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signal apbuarti : uart_in_type;
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signal apbuarto : uart_out_type;
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--MEM CTRLR
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdo : sdram_out_type;
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--IRQ
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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--Timer
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signal gpti : gptimer_in_type;
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signal gpto : gptimer_out_type;
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--GPIO
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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--DSU
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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---------------------------------------------------------------------
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--- AJOUT TEST ------------------------Signaux----------------------
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---------------------------------------------------------------------
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-- ACQ
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signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
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signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
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signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
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signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
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signal FifoF0_Empty : std_logic_vector(4 downto 0);
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signal FifoF0_Data : std_logic_vector(79 downto 0);
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signal FifoF1_Empty : std_logic_vector(4 downto 0);
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signal FifoF1_Data : std_logic_vector(79 downto 0);
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signal FifoF3_Empty : std_logic_vector(4 downto 0);
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signal FifoF3_Data : std_logic_vector(79 downto 0);
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-- MATRICE SPECTRALE
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signal SM_FlagError : std_logic;
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signal SM_Wen : std_logic;
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signal SM_Read : std_logic_vector(4 downto 0);
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signal SM_Write : std_logic_vector(1 downto 0);
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signal SM_ReUse : std_logic_vector(4 downto 0);
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signal SM_Param : std_logic_vector(3 downto 0);
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signal SM_Data : std_logic_vector(63 downto 0);
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signal FifoINT_Full : std_logic_vector(4 downto 0);
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signal FifoINT_Data : std_logic_vector(79 downto 0);
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-- FFT
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signal DMUX_Read : std_logic_vector(14 downto 0);
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signal DMUX_Empty : std_logic_vector(4 downto 0);
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signal DMUX_Data : std_logic_vector(79 downto 0);
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signal DMUX_WorkFreq : std_logic_vector(1 downto 0);
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signal FFT_Load : std_logic;
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signal FFT_Read : std_logic_vector(4 downto 0);
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signal FFT_Write : std_logic_vector(4 downto 0);
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signal FFT_ReUse : std_logic_vector(4 downto 0);
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signal FFT_Data : std_logic_vector(79 downto 0);
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signal FifoOUT_Full : std_logic_vector(1 downto 0);
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signal FifoOUT_Empty : std_logic_vector(1 downto 0);
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signal FifoOUT_Data : std_logic_vector(63 downto 0);
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--DMA
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signal DMA_Read : std_logic;
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signal DMA_ack : std_logic;
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-- Header
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signal Head_Read : std_logic_vector(1 downto 0);
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signal Head_Data : std_logic_vector(31 downto 0);
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signal Head_Empty : std_logic;
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signal Head_Header : std_logic_vector(31 DOWNTO 0);
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signal Head_Valid : std_logic;
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signal Head_Val : std_logic;
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--DAC CAL
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signal FIFOcal_Data : std_logic_vector(15 downto 0);
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signal DAC_Readn : std_logic;
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signal DAC_ReadnV : std_logic_vector(0 downto 0);
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signal clkvar : std_logic;
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--TEST DEMI-FIFO
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signal Bwr : std_logic_vector(0 downto 0);
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signal Bre : std_logic_vector(0 downto 0);
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signal DataTMP : std_logic_vector(15 downto 0);
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signal FullUp : std_logic_vector(0 downto 0);
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signal EmptyUp : std_logic_vector(0 downto 0);
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signal FullDown : std_logic_vector(0 downto 0);
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signal EmptyDown : std_logic_vector(0 downto 0);
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---------------------------------------------------------------------
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constant IOAEN : integer := CFG_CAN;
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constant boardfreq : integer := 50000;
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begin
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---------------------------------------------------------------------
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--- AJOUT TEST -------------------------------------IPs-------------
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---------------------------------------------------------------------
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-- apbo not free : 0 1 2 3 _ 7 _ 11
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-- 4 - UART
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-- 5 - FIFO CAL
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-- 6 - DAC CAL
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-- 8 - DMA
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SPW1_EN <= '1';
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SPW2_EN <= '0'; -- not SPW1_EN
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testspw1S <= clkvar;
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testspw1D <= DAC_SCLK;
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testled0 <= DAC_DATA;
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testled1 <= DAC_SYNC;
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--- ACQ -------------------------------------------------------------
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ACQ0 : lpp_top_acq
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port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3);
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Bias_Fails <= '0';
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Memf0 : lppFIFOxN
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generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
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port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
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Memf1 : lppFIFOxN
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generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
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port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
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Memf3 : lppFIFOxN
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generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
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port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
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--- FFT ------------------------------------------------------------------
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DMUX0 : DEMUX
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generic map(Data_sz => 16)
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port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data);
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FFT0 : FFT
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generic map(Data_sz => 16,NbData => 256)
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port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
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MemInt : lppFIFOxN
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generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1')
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port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
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----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
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SM0 : MatriceSpectrale
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generic map(Input_SZ => 16,Result_SZ => 32)
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port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
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MemOut : APB_FIFO
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generic map (pindex => 8, paddr => 8, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
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port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(8));
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DMA_ack <= '1';
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Head_Valid <= '1';
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-- MemOut : lppFIFOxN
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-- generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0')
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-- port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty);
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--
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------- DMA -------------------------------------------------------------
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--
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-- DMA0 : lpp_dma
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-- generic map(hindex => 2,pindex => 8, paddr => 8,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH)
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-- port map(clkm,rstn,apbi,apbo(8),ahbmi,ahbmo(2),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
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--
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------- Header ----------------------------------------------------------
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--
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-- Head0 : HeaderBuilder
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-- generic map(Data_sz => 32)
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-- port map(clkm,rstn,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
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--
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--- DAC CAL -------------------------------------------------------------
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MemCal : APB_FIFO
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generic map (pindex => 5, paddr => 5, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
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port map (clkm,rstn,clkm,clkm,(others => '0'),DAC_ReadnV,(others => '1'),open,open,FIFOcal_Data,(others => '0'),open,open,apbi,apbo(5));
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DAC_ReadnV(0) <= DAC_Readn;
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CAL0 : APB_DAC
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generic map (pindex => 6, paddr => 6, Nmax => 7)
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port map(clkm,rstn,apbi,apbo(6),FIFOcal_Data,DAC_EN,DAC_Readn,DAC_SYNC,DAC_SCLK,clkvar,DAC_DATA);
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--- UART -------------------------------------------------------------
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COM0 : APB_UART
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generic map (pindex => 4, paddr => 4)
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port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
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--- FIFO -------------------------------------------------------------
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-- Memtest : APB_FIFO
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-- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
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-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6));
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--***************************************TEST DEMI-FIFO********************************************************************************
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-- MemIn : APB_FIFO
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-- generic map (pindex => 6, paddr => 6, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
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-- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(6));
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--
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-- Pont : Bridge
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-- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
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--
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-- MemOut : APB_FIFO
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-- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
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-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
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--*************************************************************************************************************************************
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
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clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
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clkgen0 : clkgen -- clock generator
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
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port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
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ramclk <= clkm;
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process(lclk2x)
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begin
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if lclk2x'event and lclk2x = '1' then
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lclk <= not lclk;
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end if;
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end process;
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|
----------------------------------------------------------------------
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--- LEON3 processor / DSU / IRQ ------------------------------------
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----------------------------------------------------------------------
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l3 : if CFG_LEON3 = 1 generate
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cpu : for i in 0 to CFG_NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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end generate;
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errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
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dsugen : if CFG_DSU = 1 generate
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
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dsui.enable <= '1';
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dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
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dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
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end generate;
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|
end generate;
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|
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|
nodsu : if CFG_DSU = 0 generate
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|
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
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|
end generate;
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|
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|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
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irqctrl0 : irqmp -- interrupt controller
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generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
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port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
|
|
|
end generate;
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irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
|
|
x : for i in 0 to CFG_NCPU-1 generate
|
|
|
irqi(i).irl <= "0000";
|
|
|
end generate;
|
|
|
apbo(2) <= apb_none;
|
|
|
end generate;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- Memory controllers ---------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
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|
|
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
|
|
|
|
|
|
memi.brdyn <= '1'; memi.bexcn <= '1';
|
|
|
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
|
|
|
|
|
|
bdr : for i in 0 to 3 generate
|
|
|
data_pad : iopadv generic map (tech => padtech, width => 8)
|
|
|
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
|
|
|
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
|
|
|
end generate;
|
|
|
|
|
|
|
|
|
addr_pad : outpadv generic map (width => 19, tech => padtech)
|
|
|
port map (address, memo.address(20 downto 2));
|
|
|
|
|
|
|
|
|
SSRAM_0:entity ssram_plugin
|
|
|
generic map (tech => padtech)
|
|
|
port map
|
|
|
(lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- AHB CONTROLLER -------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
ahb0 : ahbctrl -- AHB arbiter/multiplexer
|
|
|
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
|
|
|
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
|
|
|
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
|
|
|
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- AHB UART -------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
dcomgen : if CFG_AHB_UART = 1 generate
|
|
|
dcom0: ahbuart -- Debug UART
|
|
|
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
|
|
|
port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
|
|
|
dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
|
|
|
dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
|
|
|
-- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
|
|
|
end generate;
|
|
|
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- APB Bridge -----------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
apb0 : apbctrl -- AHB/APB bridge
|
|
|
generic map (hindex => 1, haddr => CFG_APBADDR)
|
|
|
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- GPT Timer ------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
|
|
timer0 : gptimer -- timer unit
|
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
|
|
nbits => CFG_GPT_TW)
|
|
|
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
|
|
|
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
|
|
|
-- led(4) <= gpto.wdog;
|
|
|
end generate;
|
|
|
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
|
|
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- APB UART -------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
|
|
uart1 : apbuart -- UART 1
|
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
|
|
fifosize => CFG_UART1_FIFO)
|
|
|
port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
|
|
|
apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
|
|
|
apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
|
|
|
-- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
|
|
|
end generate;
|
|
|
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
|
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
--- GPIO -----------------------------------------------------------
|
|
|
----------------------------------------------------------------------
|
|
|
led(0) <= gpio(0); led(1) <= gpio(1);
|
|
|
|
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
|
|
|
grgpio0: grgpio
|
|
|
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
|
|
|
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
|
|
|
|
|
|
pio_pads : for i in 0 to 6 generate
|
|
|
pio_pad : iopad generic map (tech => padtech)
|
|
|
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
|
|
|
end generate;
|
|
|
end generate;
|
|
|
|
|
|
|
|
|
end Behavioral;
|
