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Update AD CONV for RHF1401 (LFR-EM) with filter
pellion -
r423:fe8f46873298 JC
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@@ -53,6 +53,8 PACKAGE lpp_ad_conv IS
53 53
54 54 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
55 55
56 SUBTYPE Samples15 IS STD_LOGIC_VECTOR(14 DOWNTO 0);
57
56 58 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
57 59
58 60 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
@@ -64,6 +66,8 PACKAGE lpp_ad_conv IS
64 66 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
65 67
66 68 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
69
70 TYPE Samples15v IS ARRAY(NATURAL RANGE <>) OF Samples15;
67 71
68 72 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
69 73
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@@ -43,7 +43,7 ARCHITECTURE ar_top_ad_conv_RHF1401 OF t
43 43 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
44 44
45 45 SIGNAL ADC_data_selected : Samples14;
46 SIGNAL ADC_data_result : Samples14;
46 SIGNAL ADC_data_result : Samples15;
47 47
48 48 SIGNAL sample_counter : INTEGER;
49 49
@@ -146,14 +146,14 BEGIN
146 146 sample_val <= '0';
147 147
148 148 CASE channel_counter IS
149 WHEN 0*2 => sample_reg(0) <= ADC_data_result;
150 WHEN 1*2 => sample_reg(1) <= ADC_data_result;
151 WHEN 2*2 => sample_reg(2) <= ADC_data_result;
152 WHEN 3*2 => sample_reg(3) <= ADC_data_result;
153 WHEN 4*2 => sample_reg(4) <= ADC_data_result;
154 WHEN 5*2 => sample_reg(5) <= ADC_data_result;
155 WHEN 6*2 => sample_reg(6) <= ADC_data_result;
156 WHEN 7*2 => sample_reg(7) <= ADC_data_result;
149 WHEN 0*2 => sample_reg(0) <= ADC_data_result(14 DOWNTO 1);
150 WHEN 1*2 => sample_reg(1) <= ADC_data_result(14 DOWNTO 1);
151 WHEN 2*2 => sample_reg(2) <= ADC_data_result(14 DOWNTO 1);
152 WHEN 3*2 => sample_reg(3) <= ADC_data_result(14 DOWNTO 1);
153 WHEN 4*2 => sample_reg(4) <= ADC_data_result(14 DOWNTO 1);
154 WHEN 5*2 => sample_reg(5) <= ADC_data_result(14 DOWNTO 1);
155 WHEN 6*2 => sample_reg(6) <= ADC_data_result(14 DOWNTO 1);
156 WHEN 7*2 => sample_reg(7) <= ADC_data_result(14 DOWNTO 1);
157 157 IF sample_counter = 9 THEN
158 158 sample_counter <= 0 ;
159 159 sample_val <= '1';
@@ -179,7 +179,7 BEGIN
179 179 sample_reg(7) WHEN OTHERS ;
180 180
181 181
182 ADC_data_result <= std_logic_vector( (signed(ADC_data_selected) + signed(ADC_data)) / 2);
182 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
183 183
184 184 sample <= sample_reg;
185 185
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