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1 lpp_fft.vhd
1 lpp_fft.vhd
2 actar.vhd
3 actram.vhd
4 CoreFFT.vhd
5 fft_components.vhd
6 fftDp.vhd
7 fftSm.vhd
8 primitives.vhd
9 twiddle.vhd
2 APB_FFT.vhd
10 APB_FFT.vhd
3 APB_FFT_half.vhd
11 APB_FFT_half.vhd
4 Driver_FFT.vhd
12 Driver_FFT.vhd
5 FFT.vhd
13 FFT.vhd
6 FFTamont.vhd
14 FFTamont.vhd
7 FFTaval.vhd
15 FFTaval.vhd
8 Flag_Extremum.vhd
16 Flag_Extremum.vhd
9 Linker_FFT.vhd
17 Linker_FFT.vhd
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@@ -1,651 +1,703
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 library ieee;
21 library ieee;
22 use ieee.std_logic_1164.all;
22 use ieee.std_logic_1164.all;
23 library grlib;
23 library grlib;
24 use grlib.amba.all;
24 use grlib.amba.all;
25 use grlib.stdlib.all;
25 use grlib.stdlib.all;
26 library techmap;
26 library techmap;
27 use techmap.gencomp.all;
27 use techmap.gencomp.all;
28 library gaisler;
28 library gaisler;
29 use gaisler.memctrl.all;
29 use gaisler.memctrl.all;
30 use gaisler.leon3.all;
30 use gaisler.leon3.all;
31 use gaisler.uart.all;
31 use gaisler.uart.all;
32 use gaisler.misc.all;
32 use gaisler.misc.all;
33 library esa;
33 library esa;
34 use esa.memoryctrl.all;
34 use esa.memoryctrl.all;
35 use work.config.all;
35 use work.config.all;
36 library lpp;
36 library lpp;
37 use lpp.lpp_amba.all;
37 use lpp.lpp_amba.all;
38 use lpp.lpp_memory.all;
38 use lpp.lpp_memory.all;
39 use lpp.lpp_uart.all;
39 use lpp.lpp_uart.all;
40 use lpp.lpp_matrix.all;
40 use lpp.lpp_matrix.all;
41 use lpp.lpp_delay.all;
41 use lpp.lpp_delay.all;
42 use lpp.lpp_fft.all;
42 use lpp.lpp_fft.all;
43 use lpp.fft_components.all;
43 use lpp.fft_components.all;
44 use lpp.lpp_ad_conv.all;
44 use lpp.lpp_ad_conv.all;
45 use lpp.iir_filter.all;
45 use lpp.iir_filter.all;
46 use lpp.general_purpose.all;
46 use lpp.general_purpose.all;
47 use lpp.Filtercfg.all;
47 use lpp.Filtercfg.all;
48 use lpp.lpp_demux.all;
48 use lpp.lpp_demux.all;
49 use lpp.lpp_top_lfr_pkg.all;
49 use lpp.lpp_top_lfr_pkg.all;
50 use lpp.lpp_dma_pkg.all;
51 use lpp.lpp_Header.all;
50
52
51 entity leon3mp is
53 entity leon3mp is
52 generic (
54 generic (
53 fabtech : integer := CFG_FABTECH;
55 fabtech : integer := CFG_FABTECH;
54 memtech : integer := CFG_MEMTECH;
56 memtech : integer := CFG_MEMTECH;
55 padtech : integer := CFG_PADTECH;
57 padtech : integer := CFG_PADTECH;
56 clktech : integer := CFG_CLKTECH;
58 clktech : integer := CFG_CLKTECH;
57 disas : integer := CFG_DISAS; -- Enable disassembly to console
59 disas : integer := CFG_DISAS; -- Enable disassembly to console
58 dbguart : integer := CFG_DUART; -- Print UART on console
60 dbguart : integer := CFG_DUART; -- Print UART on console
59 pclow : integer := CFG_PCLOW
61 pclow : integer := CFG_PCLOW
60 );
62 );
61 port (
63 port (
62 clk50MHz : in std_ulogic;
64 clk50MHz : in std_ulogic;
63 reset : in std_ulogic;
65 reset : in std_ulogic;
64 ramclk : out std_logic;
66 ramclk : out std_logic;
65
67
66 ahbrxd : in std_ulogic; -- DSU rx data
68 ahbrxd : in std_ulogic; -- DSU rx data
67 ahbtxd : out std_ulogic; -- DSU tx data
69 ahbtxd : out std_ulogic; -- DSU tx data
68 dsubre : in std_ulogic;
70 dsubre : in std_ulogic;
69 dsuact : out std_ulogic;
71 dsuact : out std_ulogic;
70 urxd1 : in std_ulogic; -- UART1 rx data
72 urxd1 : in std_ulogic; -- UART1 rx data
71 utxd1 : out std_ulogic; -- UART1 tx data
73 utxd1 : out std_ulogic; -- UART1 tx data
72 errorn : out std_ulogic;
74 errorn : out std_ulogic;
73
75
74 address : out std_logic_vector(18 downto 0);
76 address : out std_logic_vector(18 downto 0);
75 data : inout std_logic_vector(31 downto 0);
77 data : inout std_logic_vector(31 downto 0);
76 gpio : inout std_logic_vector(6 downto 0); -- I/O port
78 gpio : inout std_logic_vector(6 downto 0); -- I/O port
77
79
78 nBWa : out std_logic;
80 nBWa : out std_logic;
79 nBWb : out std_logic;
81 nBWb : out std_logic;
80 nBWc : out std_logic;
82 nBWc : out std_logic;
81 nBWd : out std_logic;
83 nBWd : out std_logic;
82 nBWE : out std_logic;
84 nBWE : out std_logic;
83 nADSC : out std_logic;
85 nADSC : out std_logic;
84 nADSP : out std_logic;
86 nADSP : out std_logic;
85 nADV : out std_logic;
87 nADV : out std_logic;
86 nGW : out std_logic;
88 nGW : out std_logic;
87 nCE1 : out std_logic;
89 nCE1 : out std_logic;
88 CE2 : out std_logic;
90 CE2 : out std_logic;
89 nCE3 : out std_logic;
91 nCE3 : out std_logic;
90 nOE : out std_logic;
92 nOE : out std_logic;
91 MODE : out std_logic;
93 MODE : out std_logic;
92 SSRAM_CLK : out std_logic;
94 SSRAM_CLK : out std_logic;
93 ZZ : out std_logic;
95 ZZ : out std_logic;
94 ---------------------------------------------------------------------
96 ---------------------------------------------------------------------
95 --- AJOUT TEST ------------------------In/Out-----------------------
97 --- AJOUT TEST ------------------------In/Out-----------------------
96 ---------------------------------------------------------------------
98 ---------------------------------------------------------------------
97 -- UART
99 -- UART
98 UART_RXD : in std_logic;
100 UART_RXD : in std_logic;
99 UART_TXD : out std_logic;
101 UART_TXD : out std_logic;
100 -- ACQ
102 -- ACQ
101 CNV_CH1 : OUT STD_LOGIC;
103 CNV_CH1 : OUT STD_LOGIC;
102 SCK_CH1 : OUT STD_LOGIC;
104 SCK_CH1 : OUT STD_LOGIC;
103 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
105 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
104 Bias_Fails : out std_logic;
106 Bias_Fails : out std_logic;
105 -- ADC
107 -- ADC
106 -- ADC_in : in AD7688_in(4 downto 0);
108 -- ADC_in : in AD7688_in(4 downto 0);
107 -- ADC_out : out AD7688_out;
109 -- ADC_out : out AD7688_out;
108
110
109 -- CNA
111 -- CNA
110 -- DAC_SYNC : out std_logic;
112 -- DAC_SYNC : out std_logic;
111 -- DAC_SCLK : out std_logic;
113 -- DAC_SCLK : out std_logic;
112 -- DAC_DATA : out std_logic;
114 -- DAC_DATA : out std_logic;
113 -- Diver
115 -- Diver
114 SPW1_EN : out std_logic;
116 SPW1_EN : out std_logic;
115 SPW2_EN : out std_logic;
117 SPW2_EN : out std_logic;
116 TEST : out std_logic_vector(3 downto 0);
118 TEST : out std_logic_vector(3 downto 0);
117
119
118 BP : in std_logic;
120 BP : in std_logic;
119 ---------------------------------------------------------------------
121 ---------------------------------------------------------------------
120 led : out std_logic_vector(1 downto 0)
122 led : out std_logic_vector(1 downto 0)
121 );
123 );
122 end;
124 end;
123
125
124 architecture Behavioral of leon3mp is
126 architecture Behavioral of leon3mp is
125
127
126 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
128 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
127 CFG_GRETH+CFG_AHB_JTAG;
129 CFG_GRETH+CFG_AHB_JTAG+1; -- +1 pour le DMA
128 constant maxahbm : integer := maxahbmsp;
130 constant maxahbm : integer := maxahbmsp;
129
131
130 --Clk & Rst g�n�
132 --Clk & Rst g�n�
131 signal vcc : std_logic_vector(4 downto 0);
133 signal vcc : std_logic_vector(4 downto 0);
132 signal gnd : std_logic_vector(4 downto 0);
134 signal gnd : std_logic_vector(4 downto 0);
133 signal resetnl : std_ulogic;
135 signal resetnl : std_ulogic;
134 signal clk2x : std_ulogic;
136 signal clk2x : std_ulogic;
135 signal lclk : std_ulogic;
137 signal lclk : std_ulogic;
136 signal lclk2x : std_ulogic;
138 signal lclk2x : std_ulogic;
137 signal clkm : std_ulogic;
139 signal clkm : std_ulogic;
138 signal rstn : std_ulogic;
140 signal rstn : std_ulogic;
139 signal rstraw : std_ulogic;
141 signal rstraw : std_ulogic;
140 signal pciclk : std_ulogic;
142 signal pciclk : std_ulogic;
141 signal sdclkl : std_ulogic;
143 signal sdclkl : std_ulogic;
142 signal cgi : clkgen_in_type;
144 signal cgi : clkgen_in_type;
143 signal cgo : clkgen_out_type;
145 signal cgo : clkgen_out_type;
144 --- AHB / APB
146 --- AHB / APB
145 signal apbi : apb_slv_in_type;
147 signal apbi : apb_slv_in_type;
146 signal apbo : apb_slv_out_vector := (others => apb_none);
148 signal apbo : apb_slv_out_vector := (others => apb_none);
147 signal ahbsi : ahb_slv_in_type;
149 signal ahbsi : ahb_slv_in_type;
148 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
150 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
149 signal ahbmi : ahb_mst_in_type;
151 signal ahbmi : ahb_mst_in_type;
150 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
152 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
151 --UART
153 --UART
152 signal ahbuarti : uart_in_type;
154 signal ahbuarti : uart_in_type;
153 signal ahbuarto : uart_out_type;
155 signal ahbuarto : uart_out_type;
154 signal apbuarti : uart_in_type;
156 signal apbuarti : uart_in_type;
155 signal apbuarto : uart_out_type;
157 signal apbuarto : uart_out_type;
156 --MEM CTRLR
158 --MEM CTRLR
157 signal memi : memory_in_type;
159 signal memi : memory_in_type;
158 signal memo : memory_out_type;
160 signal memo : memory_out_type;
159 signal wpo : wprot_out_type;
161 signal wpo : wprot_out_type;
160 signal sdo : sdram_out_type;
162 signal sdo : sdram_out_type;
161 --IRQ
163 --IRQ
162 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
164 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
163 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
165 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
164 --Timer
166 --Timer
165 signal gpti : gptimer_in_type;
167 signal gpti : gptimer_in_type;
166 signal gpto : gptimer_out_type;
168 signal gpto : gptimer_out_type;
167 --GPIO
169 --GPIO
168 signal gpioi : gpio_in_type;
170 signal gpioi : gpio_in_type;
169 signal gpioo : gpio_out_type;
171 signal gpioo : gpio_out_type;
170 --DSU
172 --DSU
171 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
173 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
172 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
174 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
173 signal dsui : dsu_in_type;
175 signal dsui : dsu_in_type;
174 signal dsuo : dsu_out_type;
176 signal dsuo : dsu_out_type;
175
177
176 ---------------------------------------------------------------------
178 ---------------------------------------------------------------------
177 --- AJOUT TEST ------------------------Signaux----------------------
179 --- AJOUT TEST ------------------------Signaux----------------------
178 ---------------------------------------------------------------------
180 ---------------------------------------------------------------------
179 -- FIFOs
181 -- FIFOs
180 signal FifoF0_Empty : std_logic_vector(4 downto 0);
182 signal FifoF0_Empty : std_logic_vector(4 downto 0);
181 signal FifoF0_Data : std_logic_vector(79 downto 0);
183 signal FifoF0_Data : std_logic_vector(79 downto 0);
182 signal FifoF1_Empty : std_logic_vector(4 downto 0);
184 signal FifoF1_Empty : std_logic_vector(4 downto 0);
183 signal FifoF1_Data : std_logic_vector(79 downto 0);
185 signal FifoF1_Data : std_logic_vector(79 downto 0);
184 signal FifoF3_Empty : std_logic_vector(4 downto 0);
186 signal FifoF3_Empty : std_logic_vector(4 downto 0);
185 signal FifoF3_Data : std_logic_vector(79 downto 0);
187 signal FifoF3_Data : std_logic_vector(79 downto 0);
186
188
187 signal FifoINT_Full : std_logic_vector(4 downto 0);
189 signal FifoINT_Full : std_logic_vector(4 downto 0);
188 signal FifoINT_Data : std_logic_vector(79 downto 0);
190 signal FifoINT_Data : std_logic_vector(79 downto 0);
189
191
190 signal FifoOUT_Full : std_logic_vector(1 downto 0);
192 signal FifoOUT_Full : std_logic_vector(1 downto 0);
193 signal FifoOUT_Empty : std_logic_vector(1 downto 0);
194 signal FifoOUT_Data : std_logic_vector(63 downto 0);
195
191
196
192 -- MATRICE SPECTRALE
197 -- MATRICE SPECTRALE
193 signal SM_FlagError : std_logic;
198 signal SM_FlagError : std_logic;
194 signal SM_Pong : std_logic;
199 signal SM_Pong : std_logic;
200 signal SM_Wen : std_logic;
195 signal SM_Read : std_logic_vector(4 downto 0);
201 signal SM_Read : std_logic_vector(4 downto 0);
196 signal SM_Write : std_logic_vector(1 downto 0);
202 signal SM_Write : std_logic_vector(1 downto 0);
197 signal SM_ReUse : std_logic_vector(4 downto 0);
203 signal SM_ReUse : std_logic_vector(4 downto 0);
198 signal SM_Param : std_logic_vector(3 downto 0);
204 signal SM_Param : std_logic_vector(3 downto 0);
199 signal SM_Data : std_logic_vector(63 downto 0);
205 signal SM_Data : std_logic_vector(63 downto 0);
200
206
201 signal Dma_acq : std_logic;
207 --signal Dma_acq : std_logic;
208 --signal Head_Valid : std_logic;
202
209
203 -- FFT
210 -- FFT
204 signal FFT_Load : std_logic;
211 signal FFT_Load : std_logic;
205 signal FFT_Read : std_logic_vector(4 downto 0);
212 signal FFT_Read : std_logic_vector(4 downto 0);
206 signal FFT_Write : std_logic_vector(4 downto 0);
213 signal FFT_Write : std_logic_vector(4 downto 0);
207 signal FFT_ReUse : std_logic_vector(4 downto 0);
214 signal FFT_ReUse : std_logic_vector(4 downto 0);
208 signal FFT_Data : std_logic_vector(79 downto 0);
215 signal FFT_Data : std_logic_vector(79 downto 0);
209
216
210 -- DEMUX
217 -- DEMUX
211 signal DEMU_Read : std_logic_vector(14 downto 0);
218 signal DMUX_Read : std_logic_vector(14 downto 0);
212 signal DEMU_Empty : std_logic_vector(4 downto 0);
219 signal DMUX_Empty : std_logic_vector(4 downto 0);
213 signal DEMU_Data : std_logic_vector(79 downto 0);
220 signal DMUX_Data : std_logic_vector(79 downto 0);
221 signal DMUX_WorkFreq : std_logic_vector(1 downto 0);
214
222
215 -- ACQ
223 -- ACQ
216 signal sample_val : STD_LOGIC;
224 signal sample_val : STD_LOGIC;
217 signal sample : Samples(8-1 DOWNTO 0);
225 signal sample : Samples(8-1 DOWNTO 0);
218
226
219 signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
227 signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
220 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
228 signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
221 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
229 signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
230 signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
223 signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
231 signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
224 signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
232 signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
233
234 -- Header
235 signal Head_Read : std_logic_vector(1 downto 0);
236 signal Head_Data : std_logic_vector(31 downto 0);
237 signal Head_Empty : std_logic;
238 signal Head_Header : std_logic_vector(31 DOWNTO 0);
239 signal Head_Valid : std_logic;
240 signal Head_Val : std_logic;
241
242 --DMA
243 signal DMA_Read : std_logic;
244 signal DMA_ack : std_logic;
245 --signal AHB_Master_In : AHB_Mst_In_Type;
246 --signal AHB_Master_Out : AHB_Mst_Out_Type;
247
225
248
226 -- ADC
249 -- ADC
227 --signal SmplClk : std_logic;
250 --signal SmplClk : std_logic;
228 --signal ADC_DataReady : std_logic;
251 --signal ADC_DataReady : std_logic;
229 --signal ADC_SmplOut : Samples_out(4 downto 0);
252 --signal ADC_SmplOut : Samples_out(4 downto 0);
230 --signal enableADC : std_logic;
253 --signal enableADC : std_logic;
231 --
254 --
232 --signal WG_Write : std_logic_vector(4 downto 0);
255 --signal WG_Write : std_logic_vector(4 downto 0);
233 --signal WG_ReUse : std_logic_vector(4 downto 0);
256 --signal WG_ReUse : std_logic_vector(4 downto 0);
234 --signal WG_DATA : std_logic_vector(79 downto 0);
257 --signal WG_DATA : std_logic_vector(79 downto 0);
235 --signal s_out : std_logic_vector(79 downto 0);
258 --signal s_out : std_logic_vector(79 downto 0);
236 --
259 --
237 --signal fuller : std_logic_vector(4 downto 0);
260 --signal fuller : std_logic_vector(4 downto 0);
238 --signal reader : std_logic_vector(4 downto 0);
261 --signal reader : std_logic_vector(4 downto 0);
239 --signal try : std_logic_vector(1 downto 0);
262 --signal try : std_logic_vector(1 downto 0);
240 --signal TXDint : std_logic;
263 --signal TXDint : std_logic;
241 --
264 --
242 ---- IIR Filter
265 ---- IIR Filter
243 --signal sample_clk_out : std_logic;
266 --signal sample_clk_out : std_logic;
244 --
267 --
245 --signal Rd : std_logic_vector(0 downto 0);
268 --signal Rd : std_logic_vector(0 downto 0);
246 --signal Ept : std_logic_vector(4 downto 0);
269 --signal Ept : std_logic_vector(4 downto 0);
247 --
270 --
248 --signal Bwr : std_logic_vector(0 downto 0);
271 --signal Bwr : std_logic_vector(0 downto 0);
249 --signal Bre : std_logic_vector(0 downto 0);
272 --signal Bre : std_logic_vector(0 downto 0);
250 --signal DataTMP : std_logic_vector(15 downto 0);
273 --signal DataTMP : std_logic_vector(15 downto 0);
251 --signal FullUp : std_logic_vector(0 downto 0);
274 --signal FullUp : std_logic_vector(0 downto 0);
252 --signal EmptyUp : std_logic_vector(0 downto 0);
275 --signal EmptyUp : std_logic_vector(0 downto 0);
253 --signal FullDown : std_logic_vector(0 downto 0);
276 --signal FullDown : std_logic_vector(0 downto 0);
254 --signal EmptyDown : std_logic_vector(0 downto 0);
277 --signal EmptyDown : std_logic_vector(0 downto 0);
255 ---------------------------------------------------------------------
278 ---------------------------------------------------------------------
256 constant IOAEN : integer := CFG_CAN;
279 constant IOAEN : integer := CFG_CAN;
257 constant boardfreq : integer := 50000;
280 constant boardfreq : integer := 50000;
258
281
259 begin
282 begin
260
283
261 ---------------------------------------------------------------------
284 ---------------------------------------------------------------------
262 --- AJOUT TEST -------------------------------------IPs-------------
285 --- AJOUT TEST -------------------------------------IPs-------------
263 ---------------------------------------------------------------------
286 ---------------------------------------------------------------------
264 led(1 downto 0) <= gpio(1 downto 0);
287 led(1 downto 0) <= gpio(1 downto 0);
265
288
266 --- COM USB ---------------------------------------------------------
289 --- COM USB ---------------------------------------------------------
267 -- MemIn0 : APB_FifoWrite
290 -- MemIn0 : APB_FifoWrite
268 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
291 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
269 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
292 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
270 --
293 --
271 -- BUF0 : APB_USB
294 -- BUF0 : APB_USB
272 -- generic map (6,6,DataMax => 1024)
295 -- generic map (6,6,DataMax => 1024)
273 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
296 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
274 --
297 --
275 -- MemOut0 : APB_FifoRead
298 -- MemOut0 : APB_FifoRead
276 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
299 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
277 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
300 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
278 --
301 --
279 --slrd <= usb_Read;
302 --slrd <= usb_Read;
280 --slwr <= usb_Write;
303 --slwr <= usb_Write;
281
304
282 --- CNA -------------------------------------------------------------
305 --- CNA -------------------------------------------------------------
283
306
284 -- CONV : APB_CNA
307 -- CONV : APB_CNA
285 -- generic map (5,5)
308 -- generic map (5,5)
286 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
309 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
287
310
288 --TEST(0) <= SmplClk;
311 --TEST(0) <= SmplClk;
289 --TEST(1) <= WG_Write(0);
312 --TEST(1) <= WG_Write(0);
290 --TEST(2) <= Fuller(0);
313 --TEST(2) <= Fuller(0);
291 --TEST(3) <= s_out(s_out'length-1);
314 --TEST(3) <= s_out(s_out'length-1);
292
315
293
316
294 --SPW1_EN <= '1';
317 --SPW1_EN <= '1';
295 --SPW2_EN <= '0';
318 --SPW2_EN <= '0';
296
319
297 --- CAN -------------------------------------------------------------
320 --- CAN -------------------------------------------------------------
298
321
299 -- Divider : Clk_divider
322 -- Divider : Clk_divider
300 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
323 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
301 -- Port map(clkm,rstn,SmplClk);
324 -- Port map(clkm,rstn,SmplClk);
302 --
325 --
303 -- ADC : AD7688_drvr
326 -- ADC : AD7688_drvr
304 -- generic map (ChanelCount => 5, clkkHz => 24_576)
327 -- generic map (ChanelCount => 5, clkkHz => 24_576)
305 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
328 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
306 --
329 --
307 -- WG : WriteGen_ADC
330 -- WG : WriteGen_ADC
308 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
331 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
309 --
332 --
310 --enableADC <= gpio(0);
333 --enableADC <= gpio(0);
311
334
312 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
335 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
313 --
336 --
314 --
337 --
315 -- MemIn1 : APB_FIFO
338 -- MemIn1 : APB_FIFO
316 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
339 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
317 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
340 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
318
341
319 -- DIGITAL_acquisition : ADS7886_drvr
342 -- DIGITAL_acquisition : ADS7886_drvr
320 -- GENERIC MAP (
343 -- GENERIC MAP (
321 -- ChanelCount => 8,
344 -- ChanelCount => 8,
322 -- ncycle_cnv_high => 79,
345 -- ncycle_cnv_high => 79,
323 -- ncycle_cnv => 500)
346 -- ncycle_cnv => 500)
324 -- PORT MAP (
347 -- PORT MAP (
325 -- cnv_clk => clk50MHz, --
348 -- cnv_clk => clk50MHz, --
326 -- cnv_rstn => rstn, --
349 -- cnv_rstn => rstn, --
327 -- cnv_run => '1', --
350 -- cnv_run => '1', --
328 -- cnv => CNV_CH1, --
351 -- cnv => CNV_CH1, --
329 -- clk => clkm, --
352 -- clk => clkm, --
330 -- rstn => rstn, --
353 -- rstn => rstn, --
331 -- sck => SCK_CH1, --
354 -- sck => SCK_CH1, --
332 -- sdo => SDO_CH1, --
355 -- sdo => SDO_CH1, --
333 -- sample => sample,
356 -- sample => sample,
334 -- sample_val => sample_val);
357 -- sample_val => sample_val);
335 --
358 --
336 --TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val;
359 --TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val;
337 --TopACQ_DataF0 <= E & D & C & B & A;
360 --TopACQ_DataF0 <= E & D & C & B & A;
338
361
339 --
362 --
340 --TEST(0) <= TopACQ_WenF0(1);
363 --TEST(0) <= TopACQ_WenF0(1);
341 --TEST(1) <= SDO_CH1(1);
364 --TEST(1) <= SDO_CH1(1);
342 --
365 --
343 --process(clkm,rstn)
366 --process(clkm,rstn)
344 --begin
367 --begin
345 -- if(rstn='0')then
368 -- if(rstn='0')then
346 -- TopACQ_WenF0a <= (others => '1');
369 -- TopACQ_WenF0a <= (others => '1');
347 --
370 --
348 -- elsif(clkm'event and clkm='1')then
371 -- elsif(clkm'event and clkm='1')then
349 -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
372 -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
350 --
373 --
351 -- end if;
374 -- end if;
352 --end process;
375 --end process;
353
376
354 TopACQ : lpp_top_acq
377 ACQ0 : lpp_top_acq
355 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
378 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3);
356
379
357 Bias_Fails <= '0';
380 Bias_Fails <= '0';
358 --- FIFO IN -------------------------------------------------------------
381 --------- FIFO IN -------------------------------------------------------------
382 ----
383 -- Memf0 : APB_FIFO
384 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
385 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF0,open,open,open,ACQ_DataF0,open,open,apbi,apbo(9));
386 --
387 -- Memf1 : APB_FIFO
388 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
389 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF1,open,open,open,ACQ_DataF1,open,open,apbi,apbo(8));
390 --
391 -- Memf3 : APB_FIFO
392 -- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
393 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF3,open,open,open,ACQ_DataF3,open,open,apbi,apbo(5));
359
394
360 -- MemOut : APB_FIFO
361 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
362 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9));
363 Memf0 : lppFIFOxN
395 Memf0 : lppFIFOxN
364 generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
396 generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
365 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
397 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
366
398
367 Memf1 : lppFIFOxN
399 Memf1 : lppFIFOxN
368 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
400 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
369 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
401 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
370
402
371 Memf3 : lppFIFOxN
403 Memf3 : lppFIFOxN
372 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
404 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
373 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
405 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
374
406 --
375 --- DEMUX -------------------------------------------------------------
407 ----- DEMUX -------------------------------------------------------------
376
408
377 DEMU0 : DEMUX
409 DMUX0 : DEMUX
378 generic map(Data_sz => 16)
410 generic map(Data_sz => 16)
379 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
411 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data);
380
412
381 --- FFT -------------------------------------------------------------
413 ------- FFT -------------------------------------------------------------
382
414
383 -- MemIn : APB_FIFO
415 -- MemIn : APB_FIFO
384 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
416 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
385 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
417 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),DMUX_Empty,open,DMUX_Data,(others => '0'),open,open,apbi,apbo(8));
386
418
387 FFT0 : FFT
419 FFT0 : FFT
388 generic map(Data_sz => 16,NbData => 256)
420 generic map(Data_sz => 16,NbData => 256)
389 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
421 port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
390
422
391 ----- LINK MEMORY -------------------------------------------------------
423 --------- LINK MEMORY -------------------------------------------------------
392
424
393 -- MemOut : APB_FIFO
425 -- MemOut : APB_FIFO
394 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
426 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
395 -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
427 -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
396
428
397 MemInt : lppFIFOxN
429 MemInt : lppFIFOxN
398 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
430 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1')
399 port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
431 port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
400 --
432
401 -- MemIn : APB_FIFO
433 -- MemIn : APB_FIFO
402 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
434 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
403 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
435 -- port map (clkm,rstn,clkm,clkm,(others => '0'),SM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
404
436
405 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
437 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
406
438
407 SM0 : MatriceSpectrale
439 SM0 : MatriceSpectrale
408 generic map(Input_SZ => 16,Result_SZ => 32)
440 generic map(Input_SZ => 16,Result_SZ => 32)
409 port map(clkm,rstn,FifoINT_Full,FFT_ReUse,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
441 port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
442
443
444 --DMA_ack <= '1';
445 --Head_Valid <= '1';
410
446
411 Dma_acq <= '1';
447 -- MemOut : APB_FIFO
448 -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
449 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
450
451 MemOut : lppFIFOxN
452 generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0')
453 port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty);
412
454
413 MemOut : APB_FIFO
455 ----------- Header -------------------------------------------------------
414 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
456
415 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
457 Head0 : HeaderBuilder
458 generic map(Data_sz => 32)
459 port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
460
461
462 --- DMA -------------------------------------------------------
463
464 DMA0 : lpp_dma
465 generic map(hindex => 1,pindex => 9, paddr => 9,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH)
466 port map(clkm,rstn,apbi,apbo(9),ahbmi,ahbmo(1),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
467
416
468
417 ----- FIFO -------------------------------------------------------------
469 ----- FIFO -------------------------------------------------------------
418
470
419 Memtest : APB_FIFO
471 -- Memtest : APB_FIFO
420 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
472 -- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
421 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
473 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
422
474
423 --***************************************TEST DEMI-FIFO********************************************************************************
475 --***************************************TEST DEMI-FIFO********************************************************************************
424 -- MemIn : APB_FIFO
476 -- MemIn : APB_FIFO
425 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
477 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
426 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
478 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
427 --
479 --
428 -- Pont : Bridge
480 -- Pont : Bridge
429 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
481 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
430 --
482 --
431 -- MemOut : APB_FIFO
483 -- MemOut : APB_FIFO
432 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
484 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
433 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
485 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
434 --*************************************************************************************************************************************
486 --*************************************************************************************************************************************
435
487
436 --- UART -------------------------------------------------------------
488 --- UART -------------------------------------------------------------
437
489
438 COM0 : APB_UART
490 COM0 : APB_UART
439 generic map (pindex => 4, paddr => 4)
491 generic map (pindex => 4, paddr => 4)
440 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
492 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
441
493
442 --- DELAY ------------------------------------------------------------
494 --- DELAY ------------------------------------------------------------
443
495
444 -- Delay0 : APB_Delay
496 -- Delay0 : APB_Delay
445 -- generic map (pindex => 4, paddr => 4)
497 -- generic map (pindex => 4, paddr => 4)
446 -- port map (clkm,rstn,apbi,apbo(4));
498 -- port map (clkm,rstn,apbi,apbo(4));
447
499
448 --- IIR Filter -------------------------------------------------------
500 --- IIR Filter -------------------------------------------------------
449 --Test(0) <= sample_clk_out;
501 --Test(0) <= sample_clk_out;
450 --
502 --
451 --
503 --
452 -- IIR1: APB_IIR_Filter
504 -- IIR1: APB_IIR_Filter
453 -- generic map(
505 -- generic map(
454 -- tech => CFG_MEMTECH,
506 -- tech => CFG_MEMTECH,
455 -- pindex => 8,
507 -- pindex => 8,
456 -- paddr => 8,
508 -- paddr => 8,
457 -- Sample_SZ => Sample_SZ,
509 -- Sample_SZ => Sample_SZ,
458 -- ChanelsCount => ChanelsCount,
510 -- ChanelsCount => ChanelsCount,
459 -- Coef_SZ => Coef_SZ,
511 -- Coef_SZ => Coef_SZ,
460 -- CoefCntPerCel => CoefCntPerCel,
512 -- CoefCntPerCel => CoefCntPerCel,
461 -- Cels_count => Cels_count,
513 -- Cels_count => Cels_count,
462 -- virgPos => virgPos
514 -- virgPos => virgPos
463 -- )
515 -- )
464 -- port map(
516 -- port map(
465 -- rst => rstn,
517 -- rst => rstn,
466 -- clk => clkm,
518 -- clk => clkm,
467 -- apbi => apbi,
519 -- apbi => apbi,
468 -- apbo => apbo(8),
520 -- apbo => apbo(8),
469 -- sample_clk_out => sample_clk_out,
521 -- sample_clk_out => sample_clk_out,
470 -- GOtest => Test(1),
522 -- GOtest => Test(1),
471 -- CoefsInitVal => (others => '1')
523 -- CoefsInitVal => (others => '1')
472 -- );
524 -- );
473 ----------------------------------------------------------------------
525 ----------------------------------------------------------------------
474
526
475 ----------------------------------------------------------------------
527 ----------------------------------------------------------------------
476 --- Reset and Clock generation -------------------------------------
528 --- Reset and Clock generation -------------------------------------
477 ----------------------------------------------------------------------
529 ----------------------------------------------------------------------
478
530
479 vcc <= (others => '1'); gnd <= (others => '0');
531 vcc <= (others => '1'); gnd <= (others => '0');
480 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
532 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
481
533
482 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
534 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
483
535
484
536
485 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
537 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
486
538
487 clkgen0 : clkgen -- clock generator
539 clkgen0 : clkgen -- clock generator
488 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
540 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
489 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
541 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
490 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
542 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
491
543
492 ramclk <= clkm;
544 ramclk <= clkm;
493 process(lclk2x)
545 process(lclk2x)
494 begin
546 begin
495 if lclk2x'event and lclk2x = '1' then
547 if lclk2x'event and lclk2x = '1' then
496 lclk <= not lclk;
548 lclk <= not lclk;
497 end if;
549 end if;
498 end process;
550 end process;
499
551
500 ----------------------------------------------------------------------
552 ----------------------------------------------------------------------
501 --- LEON3 processor / DSU / IRQ ------------------------------------
553 --- LEON3 processor / DSU / IRQ ------------------------------------
502 ----------------------------------------------------------------------
554 ----------------------------------------------------------------------
503
555
504 l3 : if CFG_LEON3 = 1 generate
556 l3 : if CFG_LEON3 = 1 generate
505 cpu : for i in 0 to CFG_NCPU-1 generate
557 cpu : for i in 0 to CFG_NCPU-1 generate
506 u0 : leon3s -- LEON3 processor
558 u0 : leon3s -- LEON3 processor
507 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
559 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
508 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
560 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
509 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
561 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
510 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
562 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
511 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
563 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
512 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
564 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
513 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
565 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
514 irqi(i), irqo(i), dbgi(i), dbgo(i));
566 irqi(i), irqo(i), dbgi(i), dbgo(i));
515 end generate;
567 end generate;
516 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
568 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
517
569
518 dsugen : if CFG_DSU = 1 generate
570 dsugen : if CFG_DSU = 1 generate
519 dsu0 : dsu3 -- LEON3 Debug Support Unit
571 dsu0 : dsu3 -- LEON3 Debug Support Unit
520 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
572 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
521 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
573 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
522 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
574 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
523 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
575 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
524 dsui.enable <= '1';
576 dsui.enable <= '1';
525 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
577 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
526 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
578 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
527 end generate;
579 end generate;
528 end generate;
580 end generate;
529
581
530 nodsu : if CFG_DSU = 0 generate
582 nodsu : if CFG_DSU = 0 generate
531 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
583 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
532 end generate;
584 end generate;
533
585
534 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
586 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
535 irqctrl0 : irqmp -- interrupt controller
587 irqctrl0 : irqmp -- interrupt controller
536 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
588 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
537 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
589 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
538 end generate;
590 end generate;
539 irq3 : if CFG_IRQ3_ENABLE = 0 generate
591 irq3 : if CFG_IRQ3_ENABLE = 0 generate
540 x : for i in 0 to CFG_NCPU-1 generate
592 x : for i in 0 to CFG_NCPU-1 generate
541 irqi(i).irl <= "0000";
593 irqi(i).irl <= "0000";
542 end generate;
594 end generate;
543 apbo(2) <= apb_none;
595 apbo(2) <= apb_none;
544 end generate;
596 end generate;
545
597
546 ----------------------------------------------------------------------
598 ----------------------------------------------------------------------
547 --- Memory controllers ---------------------------------------------
599 --- Memory controllers ---------------------------------------------
548 ----------------------------------------------------------------------
600 ----------------------------------------------------------------------
549
601
550 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
602 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
551 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
603 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
552
604
553 memi.brdyn <= '1'; memi.bexcn <= '1';
605 memi.brdyn <= '1'; memi.bexcn <= '1';
554 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
606 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
555
607
556 bdr : for i in 0 to 3 generate
608 bdr : for i in 0 to 3 generate
557 data_pad : iopadv generic map (tech => padtech, width => 8)
609 data_pad : iopadv generic map (tech => padtech, width => 8)
558 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
610 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
559 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
611 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
560 end generate;
612 end generate;
561
613
562
614
563 addr_pad : outpadv generic map (width => 19, tech => padtech)
615 addr_pad : outpadv generic map (width => 19, tech => padtech)
564 port map (address, memo.address(20 downto 2));
616 port map (address, memo.address(20 downto 2));
565
617
566
618
567 SSRAM_0:entity ssram_plugin
619 SSRAM_0:entity ssram_plugin
568 generic map (tech => padtech)
620 generic map (tech => padtech)
569 port map
621 port map
570 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
622 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
571
623
572 ----------------------------------------------------------------------
624 ----------------------------------------------------------------------
573 --- AHB CONTROLLER -------------------------------------------------
625 --- AHB CONTROLLER -------------------------------------------------
574 ----------------------------------------------------------------------
626 ----------------------------------------------------------------------
575
627
576 ahb0 : ahbctrl -- AHB arbiter/multiplexer
628 ahb0 : ahbctrl -- AHB arbiter/multiplexer
577 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
629 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
578 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
630 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
579 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
631 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
580 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
632 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
581
633
582 ----------------------------------------------------------------------
634 ----------------------------------------------------------------------
583 --- AHB UART -------------------------------------------------------
635 --- AHB UART -------------------------------------------------------
584 ----------------------------------------------------------------------
636 ----------------------------------------------------------------------
585
637
586 dcomgen : if CFG_AHB_UART = 1 generate
638 dcomgen : if CFG_AHB_UART = 1 generate
587 dcom0: ahbuart -- Debug UART
639 dcom0: ahbuart -- Debug UART
588 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
640 generic map (hindex => 2, pindex => 7, paddr => 7)
589 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
641 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(2));
590 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
642 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
591 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
643 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
592 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
644 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
593 end generate;
645 end generate;
594 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
646 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
595
647
596 ----------------------------------------------------------------------
648 ----------------------------------------------------------------------
597 --- APB Bridge -----------------------------------------------------
649 --- APB Bridge -----------------------------------------------------
598 ----------------------------------------------------------------------
650 ----------------------------------------------------------------------
599
651
600 apb0 : apbctrl -- AHB/APB bridge
652 apb0 : apbctrl -- AHB/APB bridge
601 generic map (hindex => 1, haddr => CFG_APBADDR)
653 generic map (hindex => 1, haddr => CFG_APBADDR)
602 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
654 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
603
655
604 ----------------------------------------------------------------------
656 ----------------------------------------------------------------------
605 --- GPT Timer ------------------------------------------------------
657 --- GPT Timer ------------------------------------------------------
606 ----------------------------------------------------------------------
658 ----------------------------------------------------------------------
607
659
608 gpt : if CFG_GPT_ENABLE /= 0 generate
660 gpt : if CFG_GPT_ENABLE /= 0 generate
609 timer0 : gptimer -- timer unit
661 timer0 : gptimer -- timer unit
610 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
662 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
611 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
663 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
612 nbits => CFG_GPT_TW)
664 nbits => CFG_GPT_TW)
613 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
665 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
614 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
666 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
615 -- led(4) <= gpto.wdog;
667 -- led(4) <= gpto.wdog;
616 end generate;
668 end generate;
617 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
669 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
618
670
619
671
620 ----------------------------------------------------------------------
672 ----------------------------------------------------------------------
621 --- APB UART -------------------------------------------------------
673 --- APB UART -------------------------------------------------------
622 ----------------------------------------------------------------------
674 ----------------------------------------------------------------------
623
675
624 ua1 : if CFG_UART1_ENABLE /= 0 generate
676 ua1 : if CFG_UART1_ENABLE /= 0 generate
625 uart1 : apbuart -- UART 1
677 uart1 : apbuart -- UART 1
626 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
678 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
627 fifosize => CFG_UART1_FIFO)
679 fifosize => CFG_UART1_FIFO)
628 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
680 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
629 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
681 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
630 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
682 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
631 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
683 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
632 end generate;
684 end generate;
633 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
685 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
634
686
635 ----------------------------------------------------------------------
687 ----------------------------------------------------------------------
636 --- GPIO -----------------------------------------------------------
688 --- GPIO -----------------------------------------------------------
637 ----------------------------------------------------------------------
689 ----------------------------------------------------------------------
638
690
639 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
691 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
640 grgpio0: grgpio
692 grgpio0: grgpio
641 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
693 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
642 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
694 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
643
695
644 pio_pads : for i in 0 to 6 generate
696 pio_pads : for i in 0 to 6 generate
645 pio_pad : iopad generic map (tech => padtech)
697 pio_pad : iopad generic map (tech => padtech)
646 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
698 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
647 end generate;
699 end generate;
648 end generate;
700 end generate;
649
701
650
702
651 end Behavioral; No newline at end of file
703 end Behavioral;
Show file before | Show file after | Hide comments
@@ -1,211 +1,211
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_dma_apbreg IS
37 ENTITY lpp_dma_apbreg IS
38 GENERIC (
38 GENERIC (
39 pindex : INTEGER := 4;
39 pindex : INTEGER := 4;
40 paddr : INTEGER := 4;
40 paddr : INTEGER := 4;
41 pmask : INTEGER := 16#fff#;
41 pmask : INTEGER := 16#fff#;
42 pirq : INTEGER := 0);
42 pirq : INTEGER := 0);
43 PORT (
43 PORT (
44 -- AMBA AHB system signals
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
47
48 -- AMBA APB Slave Interface
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
50 apbo : OUT apb_slv_out_type;
51
51
52 -- IN
52 -- IN
53 ready_matrix_f0_0 : IN STD_LOGIC;
53 ready_matrix_f0_0 : IN STD_LOGIC;
54 ready_matrix_f0_1 : IN STD_LOGIC;
54 ready_matrix_f0_1 : IN STD_LOGIC;
55 ready_matrix_f1 : IN STD_LOGIC;
55 ready_matrix_f1 : IN STD_LOGIC;
56 ready_matrix_f2 : IN STD_LOGIC;
56 ready_matrix_f2 : IN STD_LOGIC;
57 error_anticipating_empty_fifo : IN STD_LOGIC;
57 error_anticipating_empty_fifo : IN STD_LOGIC;
58 error_bad_component_error : IN STD_LOGIC;
58 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60
60
61 -- OUT
61 -- OUT
62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
64 status_ready_matrix_f1 : OUT STD_LOGIC;
64 status_ready_matrix_f1 : OUT STD_LOGIC;
65 status_ready_matrix_f2 : OUT STD_LOGIC;
65 status_ready_matrix_f2 : OUT STD_LOGIC;
66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
67 status_error_bad_component_error : OUT STD_LOGIC;
67 status_error_bad_component_error : OUT STD_LOGIC;
68
68
69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
70 config_active_interruption_onError : OUT STD_LOGIC;
70 config_active_interruption_onError : OUT STD_LOGIC;
71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
75 );
75 );
76
76
77 END lpp_dma_apbreg;
77 END lpp_dma_apbreg;
78
78
79 ARCHITECTURE beh OF lpp_dma_apbreg IS
79 ARCHITECTURE beh OF lpp_dma_apbreg IS
80
80
81 CONSTANT REVISION : INTEGER := 1;
81 CONSTANT REVISION : INTEGER := 1;
82
82
83 CONSTANT pconfig : apb_config_type := (
83 CONSTANT pconfig : apb_config_type := (
84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
85 1 => apb_iobar(paddr, pmask));
85 1 => apb_iobar(paddr, pmask));
86
86
87 TYPE lpp_dma_regs IS RECORD
87 TYPE lpp_dma_regs IS RECORD
88 config_active_interruption_onNewMatrix : STD_LOGIC;
88 config_active_interruption_onNewMatrix : STD_LOGIC;
89 config_active_interruption_onError : STD_LOGIC;
89 config_active_interruption_onError : STD_LOGIC;
90 status_ready_matrix_f0_0 : STD_LOGIC;
90 status_ready_matrix_f0_0 : STD_LOGIC;
91 status_ready_matrix_f0_1 : STD_LOGIC;
91 status_ready_matrix_f0_1 : STD_LOGIC;
92 status_ready_matrix_f1 : STD_LOGIC;
92 status_ready_matrix_f1 : STD_LOGIC;
93 status_ready_matrix_f2 : STD_LOGIC;
93 status_ready_matrix_f2 : STD_LOGIC;
94 status_error_anticipating_empty_fifo : STD_LOGIC;
94 status_error_anticipating_empty_fifo : STD_LOGIC;
95 status_error_bad_component_error : STD_LOGIC;
95 status_error_bad_component_error : STD_LOGIC;
96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 END RECORD;
100 END RECORD;
101
101
102 SIGNAL reg : lpp_dma_regs;
102 SIGNAL reg : lpp_dma_regs;
103
103
104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105
105
106 BEGIN -- beh
106 BEGIN -- beh
107
107
108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
113 status_error_bad_component_error <= reg.status_error_bad_component_error;
113 status_error_bad_component_error <= reg.status_error_bad_component_error;
114
114
115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
116 config_active_interruption_onError <= reg.config_active_interruption_onError;
116 config_active_interruption_onError <= reg.config_active_interruption_onError;
117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
119 addr_matrix_f1 <= reg.addr_matrix_f1;
119 addr_matrix_f1 <= reg.addr_matrix_f1;
120 addr_matrix_f2 <= reg.addr_matrix_f2;
120 addr_matrix_f2 <= reg.addr_matrix_f2;
121
121
122 lpp_dma_apbreg : PROCESS (HCLK, HRESETn)
122 lpp_dma_apbreg : PROCESS (HCLK, HRESETn)
123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
124 BEGIN -- PROCESS lpp_dma_top
124 BEGIN -- PROCESS lpp_dma_top
125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
126 reg.config_active_interruption_onNewMatrix <= '0';
126 reg.config_active_interruption_onNewMatrix <= '0';
127 reg.config_active_interruption_onError <= '0';
127 reg.config_active_interruption_onError <= '0';
128 reg.status_ready_matrix_f0_0 <= '0';
128 reg.status_ready_matrix_f0_0 <= '0';
129 reg.status_ready_matrix_f0_1 <= '0';
129 reg.status_ready_matrix_f0_1 <= '0';
130 reg.status_ready_matrix_f1 <= '0';
130 reg.status_ready_matrix_f1 <= '0';
131 reg.status_ready_matrix_f2 <= '0';
131 reg.status_ready_matrix_f2 <= '0';
132 reg.status_error_anticipating_empty_fifo <= '0';
132 reg.status_error_anticipating_empty_fifo <= '0';
133 reg.status_error_bad_component_error <= '0';
133 reg.status_error_bad_component_error <= '0';
134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
136 reg.addr_matrix_f1 <= (OTHERS => '0');
136 reg.addr_matrix_f1 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
140
140
141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
142 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
142 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
143 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
143 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
144 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
144 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
145
145
146 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
146 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
147 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
147 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
148
148
149 paddr := "000000";
149 paddr := "000000";
150 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
150 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
151 prdata <= (OTHERS => '0');
151 prdata <= (OTHERS => '0');
152 IF apbi.psel(pindex) = '1' THEN
152 IF apbi.psel(pindex) = '1' THEN
153 -- APB DMA READ --
153 -- APB DMA READ --
154 CASE paddr(7 DOWNTO 2) IS
154 CASE paddr(7 DOWNTO 2) IS
155 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
155 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
156 prdata(1) <= reg.config_active_interruption_onError;
156 prdata(1) <= reg.config_active_interruption_onError;
157 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
157 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
158 prdata(1) <= reg.status_ready_matrix_f0_1;
158 prdata(1) <= reg.status_ready_matrix_f0_1;
159 prdata(2) <= reg.status_ready_matrix_f1;
159 prdata(2) <= reg.status_ready_matrix_f1;
160 prdata(3) <= reg.status_ready_matrix_f2;
160 prdata(3) <= reg.status_ready_matrix_f2;
161 prdata(4) <= reg.status_error_anticipating_empty_fifo;
161 prdata(4) <= reg.status_error_anticipating_empty_fifo;
162 prdata(5) <= reg.status_error_bad_component_error;
162 prdata(5) <= reg.status_error_bad_component_error;
163 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
163 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 WHEN "000110" => prdata <= debug_reg;
167 WHEN "000110" => prdata <= debug_reg;
168 WHEN OTHERS => NULL;
168 WHEN OTHERS => NULL;
169 END CASE;
169 END CASE;
170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
171 -- APB DMA WRITE --
171 -- APB DMA WRITE --
172 CASE paddr(7 DOWNTO 2) IS
172 CASE paddr(7 DOWNTO 2) IS
173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
174 reg.config_active_interruption_onError <= apbi.pwdata(1);
174 reg.config_active_interruption_onError <= apbi.pwdata(1);
175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
180 reg.status_error_bad_component_error <= apbi.pwdata(5);
180 reg.status_error_bad_component_error <= apbi.pwdata(5);
181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
185 WHEN OTHERS => NULL;
185 WHEN OTHERS => NULL;
186 END CASE;
186 END CASE;
187 END IF;
187 END IF;
188 END IF;
188 END IF;
189 END IF;
189 END IF;
190 END PROCESS lpp_dma_apbreg;
190 END PROCESS lpp_dma_apbreg;
191
191
192 apbo.pirq <= (reg.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
192 apbo.pirq(pirq) <= (reg.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
193 ready_matrix_f0_1 OR
193 ready_matrix_f0_1 OR
194 ready_matrix_f1 OR
194 ready_matrix_f1 OR
195 ready_matrix_f2)
195 ready_matrix_f2)
196 )
196 )
197 OR
197 OR
198 (reg.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
198 (reg.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
199 error_bad_component_error)
199 error_bad_component_error)
200 );
200 );
201
201
202
202
203
203
204
204
205
205
206 apbo.pindex <= pindex;
206 apbo.pindex <= pindex;
207 apbo.pconfig <= pconfig;
207 apbo.pconfig <= pconfig;
208 apbo.prdata <= prdata;
208 apbo.prdata <= prdata;
209
209
210
210
211 END beh;
211 END beh; No newline at end of file
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@@ -1,13 +1,14
1 ALU_Driver.vhd
1 ALU_Driver.vhd
2 APB_Matrix.vhd
2 APB_Matrix.vhd
3 ReUse_CTRLR.vhd
3 Dispatch.vhd
4 Dispatch.vhd
4 DriveInputs.vhd
5 DriveInputs.vhd
5 GetResult.vhd
6 GetResult.vhd
6 MatriceSpectrale.vhd
7 MatriceSpectrale.vhd
7 Matrix.vhd
8 Matrix.vhd
8 SpectralMatrix.vhd
9 SpectralMatrix.vhd
9 Starter.vhd
10 Starter.vhd
10 TopMatrix_PDR.vhd
11 TopMatrix_PDR.vhd
11 TopSpecMatrix.vhd
12 TopSpecMatrix.vhd
12 Top_MatrixSpec.vhd
13 Top_MatrixSpec.vhd
13 lpp_matrix.vhd
14 lpp_matrix.vhd
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@@ -1,7 +1,8
1 lpp_memory.vhd
1 lpp_memory.vhd
2 lpp_FIFO.vhd
2 lpp_FIFO.vhd
3 FillFifo.vhd
3 APB_FIFO.vhd
4 APB_FIFO.vhd
4 Bridge.vhd
5 Bridge.vhd
5 SSRAM_plugin.vhd
6 SSRAM_plugin.vhd
6 lppFIFOx5.vhd
7 lppFIFOx5.vhd
7 lppFIFOxN.vhd
8 lppFIFOxN.vhd
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@@ -1,7 +1,8
1 lpp_top_lfr_pkg.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_top_apbreg.vhd
2 lpp_top_apbreg.vhd
3 lpp_top_acq.vhd
3 lpp_top_lfr_wf_picker.vhd
4 lpp_top_lfr_wf_picker.vhd
4 lpp_top_lfr_wf_picker_ip.vhd
5 lpp_top_lfr_wf_picker_ip.vhd
5 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
6 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
6 top_lfr_wf_picker.vhd
7 top_lfr_wf_picker.vhd
7 top_wf_picker.vhd
8 top_wf_picker.vhd
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