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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 --library proasic3l;
48 --library proasic3l;
49 --use proasic3l.all;
49 --use proasic3l.all;
50
50
51 ENTITY LFR_EQM IS
51 ENTITY LFR_EQM IS
52 --GENERIC (
52 --GENERIC (
53 -- Mem_use : INTEGER := use_RAM);
53 -- Mem_use : INTEGER := use_RAM);
54
54
55 PORT (
55 PORT (
56 clk50MHz : IN STD_ULOGIC;
56 clk50MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
59
60 -- TAG --------------------------------------------------------------------
60 -- TAG --------------------------------------------------------------------
61 TAG1 : IN STD_ULOGIC; -- DSU rx data
61 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 -- UART APB ---------------------------------------------------------------
63 -- UART APB ---------------------------------------------------------------
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 -- RAM --------------------------------------------------------------------
66 -- RAM --------------------------------------------------------------------
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69
69
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 nSRAM_E1 : OUT STD_LOGIC; -- new
71 nSRAM_E1 : OUT STD_LOGIC; -- new
72 nSRAM_E2 : OUT STD_LOGIC; -- new
72 nSRAM_E2 : OUT STD_LOGIC; -- new
73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 nSRAM_W : OUT STD_LOGIC; -- new
74 nSRAM_W : OUT STD_LOGIC; -- new
75 nSRAM_G : OUT STD_LOGIC; -- new
75 nSRAM_G : OUT STD_LOGIC; -- new
76 nSRAM_BUSY : IN STD_LOGIC; -- new
76 nSRAM_BUSY : IN STD_LOGIC; -- new
77 -- SPW --------------------------------------------------------------------
77 -- SPW --------------------------------------------------------------------
78 spw1_en : OUT STD_LOGIC; -- new
78 spw1_en : OUT STD_LOGIC; -- new
79 spw1_din : IN STD_LOGIC;
79 spw1_din : IN STD_LOGIC;
80 spw1_sin : IN STD_LOGIC;
80 spw1_sin : IN STD_LOGIC;
81 spw1_dout : OUT STD_LOGIC;
81 spw1_dout : OUT STD_LOGIC;
82 spw1_sout : OUT STD_LOGIC;
82 spw1_sout : OUT STD_LOGIC;
83 spw2_en : OUT STD_LOGIC; -- new
83 spw2_en : OUT STD_LOGIC; -- new
84 spw2_din : IN STD_LOGIC;
84 spw2_din : IN STD_LOGIC;
85 spw2_sin : IN STD_LOGIC;
85 spw2_sin : IN STD_LOGIC;
86 spw2_dout : OUT STD_LOGIC;
86 spw2_dout : OUT STD_LOGIC;
87 spw2_sout : OUT STD_LOGIC;
87 spw2_sout : OUT STD_LOGIC;
88 -- ADC --------------------------------------------------------------------
88 -- ADC --------------------------------------------------------------------
89 bias_fail_sw : OUT STD_LOGIC;
89 bias_fail_sw : OUT STD_LOGIC;
90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 ADC_smpclk : OUT STD_LOGIC;
91 ADC_smpclk : OUT STD_LOGIC;
92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 -- DAC --------------------------------------------------------------------
93 -- DAC --------------------------------------------------------------------
94 DAC_SDO : OUT STD_LOGIC;
94 DAC_SDO : OUT STD_LOGIC;
95 DAC_SCK : OUT STD_LOGIC;
95 DAC_SCK : OUT STD_LOGIC;
96 DAC_SYNC : OUT STD_LOGIC;
96 DAC_SYNC : OUT STD_LOGIC;
97 DAC_CAL_EN : OUT STD_LOGIC;
97 DAC_CAL_EN : OUT STD_LOGIC;
98 -- HK ---------------------------------------------------------------------
98 -- HK ---------------------------------------------------------------------
99 HK_smpclk : OUT STD_LOGIC;
99 HK_smpclk : OUT STD_LOGIC;
100 ADC_OEB_bar_HK : OUT STD_LOGIC;
100 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 ---------------------------------------------------------------------------
102 ---------------------------------------------------------------------------
103 TAG8 : OUT STD_LOGIC
103 TAG8 : OUT STD_LOGIC
104 );
104 );
105
105
106 END LFR_EQM;
106 END LFR_EQM;
107
107
108
108
109 ARCHITECTURE beh OF LFR_EQM IS
109 ARCHITECTURE beh OF LFR_EQM IS
110
110
111 SIGNAL clk_25 : STD_LOGIC := '0';
111 SIGNAL clk_25 : STD_LOGIC := '0';
112 SIGNAL clk_24 : STD_LOGIC := '0';
112 SIGNAL clk_24 : STD_LOGIC := '0';
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116
116
117 -- CONSTANTS
117 -- CONSTANTS
118 CONSTANT CFG_PADTECH : INTEGER := inferred;
118 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
122
122
123 SIGNAL apbi_ext : apb_slv_in_type;
123 SIGNAL apbi_ext : apb_slv_in_type;
124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129
129
130 -- Spacewire signals
130 -- Spacewire signals
131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL spw_rxtxclk : STD_ULOGIC;
134 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 SIGNAL spw_rxclkn : STD_ULOGIC;
135 SIGNAL spw_rxclkn : STD_ULOGIC;
136 SIGNAL spw_clk : STD_LOGIC;
136 SIGNAL spw_clk : STD_LOGIC;
137 SIGNAL swni : grspw_in_type;
137 SIGNAL swni : grspw_in_type;
138 SIGNAL swno : grspw_out_type;
138 SIGNAL swno : grspw_out_type;
139
139
140 --GPIO
140 --GPIO
141 SIGNAL gpioi : gpio_in_type;
141 SIGNAL gpioi : gpio_in_type;
142 SIGNAL gpioo : gpio_out_type;
142 SIGNAL gpioo : gpio_out_type;
143
143
144 -- AD Converter ADS7886
144 -- AD Converter ADS7886
145 SIGNAL sample : Samples14v(8 DOWNTO 0);
145 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 SIGNAL sample_s : Samples(8 DOWNTO 0);
146 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 SIGNAL sample_val : STD_LOGIC;
147 SIGNAL sample_val : STD_LOGIC;
148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149
149
150 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 SIGNAL rstn_25 : STD_LOGIC;
154 SIGNAL rstn_25 : STD_LOGIC;
155 SIGNAL rstn_24 : STD_LOGIC;
155 SIGNAL rstn_24 : STD_LOGIC;
156
156
157 SIGNAL LFR_soft_rstn : STD_LOGIC;
157 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 SIGNAL LFR_rstn : STD_LOGIC;
158 SIGNAL LFR_rstn : STD_LOGIC;
159
159
160 SIGNAL ADC_smpclk_s : STD_LOGIC;
160 SIGNAL ADC_smpclk_s : STD_LOGIC;
161
161
162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163
163
164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
166
166
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168
168
169 SIGNAL rstn_50 : STD_LOGIC;
170 SIGNAL clk_lock : STD_LOGIC;
171 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
173
174 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL ahbrxd: STD_LOGIC;
176 SIGNAL ahbtxd: STD_LOGIC;
177 SIGNAL urxd1 : STD_LOGIC;
178 SIGNAL utxd1 : STD_LOGIC;
169 BEGIN -- beh
179 BEGIN -- beh
170
180
171 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK_LOCK
183 -----------------------------------------------------------------------------
184 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
185
186 PROCESS (clk50MHz_int, rstn_50)
187 BEGIN -- PROCESS
188 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
189 clk_lock <= '0';
190 clk_busy_counter <= (OTHERS => '0');
191 nSRAM_BUSY_reg <= '0';
192 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
193 nSRAM_BUSY_reg <= nSRAM_BUSY;
194 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
195 IF clk_busy_counter = "1111" THEN
196 clk_lock <= '1';
197 ELSE
198 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
199 END IF;
200 END IF;
201 END IF;
202 END PROCESS;
203
204 -----------------------------------------------------------------------------
172 -- CLK
205 -- CLK
173 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
207 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
208 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
176
209
177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
210 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 clk50MHz_int <= clk50MHz;
211 clk50MHz_int <= clk50MHz;
179
212
180 PROCESS(clk50MHz_int)
213 PROCESS(clk50MHz_int)
181 BEGIN
214 BEGIN
182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
215 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
183 --clk_25_int <= NOT clk_25_int;
216 --clk_25_int <= NOT clk_25_int;
184 clk_25 <= NOT clk_25;
217 clk_25 <= NOT clk_25;
185 END IF;
218 END IF;
186 END PROCESS;
219 END PROCESS;
187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
220 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
188
221
189 PROCESS(clk49_152MHz)
222 PROCESS(clk49_152MHz)
190 BEGIN
223 BEGIN
191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
224 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 clk_24 <= NOT clk_24;
225 clk_24 <= NOT clk_24;
193 END IF;
226 END IF;
194 END PROCESS;
227 END PROCESS;
195
228
196 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
197 --
230 --
198 leon3_soc_1 : leon3_soc
231 leon3_soc_1 : leon3_soc
199 GENERIC MAP (
232 GENERIC MAP (
200 fabtech => apa3l,
233 fabtech => apa3l,
201 memtech => apa3l,
234 memtech => apa3l,
202 padtech => inferred,
235 padtech => inferred,
203 clktech => inferred,
236 clktech => inferred,
204 disas => 0,
237 disas => 0,
205 dbguart => 0,
238 dbguart => 0,
206 pclow => 2,
239 pclow => 2,
207 clk_freq => 25000,
240 clk_freq => 25000,
208 IS_RADHARD => 0,
241 IS_RADHARD => 0,
209 NB_CPU => 1,
242 NB_CPU => 1,
210 ENABLE_FPU => 1,
243 ENABLE_FPU => 1,
211 FPU_NETLIST => 0,
244 FPU_NETLIST => 0,
212 ENABLE_DSU => 1,
245 ENABLE_DSU => 1,
213 ENABLE_AHB_UART => 1,
246 ENABLE_AHB_UART => 1,
214 ENABLE_APB_UART => 1,
247 ENABLE_APB_UART => 1,
215 ENABLE_IRQMP => 1,
248 ENABLE_IRQMP => 1,
216 ENABLE_GPT => 1,
249 ENABLE_GPT => 1,
217 NB_AHB_MASTER => NB_AHB_MASTER,
250 NB_AHB_MASTER => NB_AHB_MASTER,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
251 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
252 NB_APB_SLAVE => NB_APB_SLAVE,
220 ADDRESS_SIZE => 19,
253 ADDRESS_SIZE => 19,
221 USES_IAP_MEMCTRLR => 1,
254 USES_IAP_MEMCTRLR => 1,
222 BYPASS_EDAC_MEMCTRLR => '0',
255 BYPASS_EDAC_MEMCTRLR => '0',
223 SRBANKSZ => 8)
256 SRBANKSZ => 8)
224 PORT MAP (
257 PORT MAP (
225 clk => clk_25,
258 clk => clk_25,
226 reset => rstn_25,
259 reset => rstn_25,
227 errorn => OPEN,
260 errorn => OPEN,
228
261
229 ahbrxd => TAG1,
262 ahbrxd => TAG1,
230 ahbtxd => TAG3,
263 ahbtxd => TAG3,
231 urxd1 => TAG2,
264 urxd1 => TAG2,
232 utxd1 => TAG4,
265 utxd1 => TAG4,
233
266
234 address => address,
267 address => address,
235 data => data,
268 data => data,
236 nSRAM_BE0 => OPEN,
269 nSRAM_BE0 => OPEN,
237 nSRAM_BE1 => OPEN,
270 nSRAM_BE1 => OPEN,
238 nSRAM_BE2 => OPEN,
271 nSRAM_BE2 => OPEN,
239 nSRAM_BE3 => OPEN,
272 nSRAM_BE3 => OPEN,
240 nSRAM_WE => nSRAM_W,
273 nSRAM_WE => nSRAM_W,
241 nSRAM_CE => nSRAM_CE,
274 nSRAM_CE => nSRAM_CE,
242 nSRAM_OE => nSRAM_G,
275 nSRAM_OE => nSRAM_G,
243 nSRAM_READY => nSRAM_BUSY,
276 nSRAM_READY => nSRAM_BUSY,
244 SRAM_MBE => nSRAM_MBE,
277 SRAM_MBE => nSRAM_MBE,
245
278
246 apbi_ext => apbi_ext,
279 apbi_ext => apbi_ext,
247 apbo_ext => apbo_ext,
280 apbo_ext => apbo_ext,
248 ahbi_s_ext => ahbi_s_ext,
281 ahbi_s_ext => ahbi_s_ext,
249 ahbo_s_ext => ahbo_s_ext,
282 ahbo_s_ext => ahbo_s_ext,
250 ahbi_m_ext => ahbi_m_ext,
283 ahbi_m_ext => ahbi_m_ext,
251 ahbo_m_ext => ahbo_m_ext);
284 ahbo_m_ext => ahbo_m_ext);
252
285
253
286
254 nSRAM_E1 <= nSRAM_CE(0);
287 nSRAM_E1 <= nSRAM_CE(0);
255 nSRAM_E2 <= nSRAM_CE(1);
288 nSRAM_E2 <= nSRAM_CE(1);
256
289
257 -------------------------------------------------------------------------------
290 -------------------------------------------------------------------------------
258 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
291 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
259 -------------------------------------------------------------------------------
292 -------------------------------------------------------------------------------
260 apb_lfr_management_1 : apb_lfr_management
293 apb_lfr_management_1 : apb_lfr_management
261 GENERIC MAP (
294 GENERIC MAP (
262 tech => apa3l,
295 tech => apa3l,
263 pindex => 6,
296 pindex => 6,
264 paddr => 6,
297 paddr => 6,
265 pmask => 16#fff#,
298 pmask => 16#fff#,
266 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
299 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
267 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
300 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
268 PORT MAP (
301 PORT MAP (
269 clk25MHz => clk_25,
302 clk25MHz => clk_25,
270 resetn_25MHz => rstn_25, -- TODO
303 resetn_25MHz => rstn_25, -- TODO
271 --clk24_576MHz => clk_24, -- 49.152MHz/2
304 --clk24_576MHz => clk_24, -- 49.152MHz/2
272 --resetn_24_576MHz => rstn_24, -- TODO
305 --resetn_24_576MHz => rstn_24, -- TODO
273
306
274 grspw_tick => swno.tickout,
307 grspw_tick => swno.tickout,
275 apbi => apbi_ext,
308 apbi => apbi_ext,
276 apbo => apbo_ext(6),
309 apbo => apbo_ext(6),
277
310
278 HK_sample => sample_s(8),
311 HK_sample => sample_s(8),
279 HK_val => sample_val,
312 HK_val => sample_val,
280 HK_sel => HK_SEL,
313 HK_sel => HK_SEL,
281
314
282 DAC_SDO => DAC_SDO,
315 DAC_SDO => DAC_SDO,
283 DAC_SCK => DAC_SCK,
316 DAC_SCK => DAC_SCK,
284 DAC_SYNC => DAC_SYNC,
317 DAC_SYNC => DAC_SYNC,
285 DAC_CAL_EN => DAC_CAL_EN,
318 DAC_CAL_EN => DAC_CAL_EN,
286
319
287 coarse_time => coarse_time,
320 coarse_time => coarse_time,
288 fine_time => fine_time,
321 fine_time => fine_time,
289 LFR_soft_rstn => LFR_soft_rstn
322 LFR_soft_rstn => LFR_soft_rstn
290 );
323 );
291
324
292 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
293 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
294 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
295
328
296 ------------------------------------------------------------------------------
329 ------------------------------------------------------------------------------
297 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
330 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
298 ------------------------------------------------------------------------------
331 ------------------------------------------------------------------------------
299 spw1_en <= '1';
332 spw1_en <= '1';
300 spw2_en <= '1';
333 spw2_en <= '1';
301 ------------------------------------------------------------------------------
334 ------------------------------------------------------------------------------
302 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
335 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
303 ------------------------------------------------------------------------------
336 ------------------------------------------------------------------------------
304
337
305 --spw_clk <= clk50MHz;
338 --spw_clk <= clk50MHz;
306 --spw_rxtxclk <= spw_clk;
339 --spw_rxtxclk <= spw_clk;
307 --spw_rxclkn <= NOT spw_rxtxclk;
340 --spw_rxclkn <= NOT spw_rxtxclk;
308
341
309 -- PADS for SPW1
342 -- PADS for SPW1
310 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
343 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
311 PORT MAP (spw1_din, dtmp(0));
344 PORT MAP (spw1_din, dtmp(0));
312 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
345 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
313 PORT MAP (spw1_sin, stmp(0));
346 PORT MAP (spw1_sin, stmp(0));
314 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
347 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
315 PORT MAP (spw1_dout, swno.d(0));
348 PORT MAP (spw1_dout, swno.d(0));
316 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
349 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
317 PORT MAP (spw1_sout, swno.s(0));
350 PORT MAP (spw1_sout, swno.s(0));
318 -- PADS FOR SPW2
351 -- PADS FOR SPW2
319 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
352 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 PORT MAP (spw2_din, dtmp(1));
353 PORT MAP (spw2_din, dtmp(1));
321 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
354 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
322 PORT MAP (spw2_sin, stmp(1));
355 PORT MAP (spw2_sin, stmp(1));
323 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
356 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
324 PORT MAP (spw2_dout, swno.d(1));
357 PORT MAP (spw2_dout, swno.d(1));
325 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
358 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
326 PORT MAP (spw2_sout, swno.s(1));
359 PORT MAP (spw2_sout, swno.s(1));
327
360
328 -- GRSPW PHY
361 -- GRSPW PHY
329 --spw1_input: if CFG_SPW_GRSPW = 1 generate
362 --spw1_input: if CFG_SPW_GRSPW = 1 generate
330 spw_inputloop : FOR j IN 0 TO 1 GENERATE
363 spw_inputloop : FOR j IN 0 TO 1 GENERATE
331 spw_phy0 : grspw_phy
364 spw_phy0 : grspw_phy
332 GENERIC MAP(
365 GENERIC MAP(
333 tech => apa3l,
366 tech => apa3l,
334 rxclkbuftype => 1,
367 rxclkbuftype => 1,
335 scantest => 0)
368 scantest => 0)
336 PORT MAP(
369 PORT MAP(
337 rxrst => swno.rxrst,
370 rxrst => swno.rxrst,
338 di => dtmp(j),
371 di => dtmp(j),
339 si => stmp(j),
372 si => stmp(j),
340 rxclko => spw_rxclk(j),
373 rxclko => spw_rxclk(j),
341 do => swni.d(j),
374 do => swni.d(j),
342 ndo => swni.nd(j*5+4 DOWNTO j*5),
375 ndo => swni.nd(j*5+4 DOWNTO j*5),
343 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
376 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
344 END GENERATE spw_inputloop;
377 END GENERATE spw_inputloop;
345
378
346 -- SPW core
379 -- SPW core
347 sw0 : grspwm GENERIC MAP(
380 sw0 : grspwm GENERIC MAP(
348 tech => apa3l,
381 tech => apa3l,
349 hindex => 1,
382 hindex => 1,
350 pindex => 5,
383 pindex => 5,
351 paddr => 5,
384 paddr => 5,
352 pirq => 11,
385 pirq => 11,
353 sysfreq => 25000, -- CPU_FREQ
386 sysfreq => 25000, -- CPU_FREQ
354 rmap => 1,
387 rmap => 1,
355 rmapcrc => 1,
388 rmapcrc => 1,
356 fifosize1 => 16,
389 fifosize1 => 16,
357 fifosize2 => 16,
390 fifosize2 => 16,
358 rxclkbuftype => 1,
391 rxclkbuftype => 1,
359 rxunaligned => 0,
392 rxunaligned => 0,
360 rmapbufs => 4,
393 rmapbufs => 4,
361 ft => 0,
394 ft => 0,
362 netlist => 0,
395 netlist => 0,
363 ports => 2,
396 ports => 2,
364 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
397 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
365 memtech => apa3l,
398 memtech => apa3l,
366 destkey => 2,
399 destkey => 2,
367 spwcore => 1
400 spwcore => 1
368 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
401 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
369 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
402 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
370 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
403 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
371 )
404 )
372 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
405 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
373 spw_rxclk(1),
406 spw_rxclk(1),
374 clk50MHz_int,
407 clk50MHz_int,
375 clk50MHz_int,
408 clk50MHz_int,
376 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
409 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
377 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
410 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
378 swni, swno);
411 swni, swno);
379
412
380 swni.tickin <= '0';
413 swni.tickin <= '0';
381 swni.rmapen <= '1';
414 swni.rmapen <= '1';
382 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
415 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
383 swni.tickinraw <= '0';
416 swni.tickinraw <= '0';
384 swni.timein <= (OTHERS => '0');
417 swni.timein <= (OTHERS => '0');
385 swni.dcrstval <= (OTHERS => '0');
418 swni.dcrstval <= (OTHERS => '0');
386 swni.timerrstval <= (OTHERS => '0');
419 swni.timerrstval <= (OTHERS => '0');
387
420
388 -------------------------------------------------------------------------------
421 -------------------------------------------------------------------------------
389 -- LFR ------------------------------------------------------------------------
422 -- LFR ------------------------------------------------------------------------
390 -------------------------------------------------------------------------------
423 -------------------------------------------------------------------------------
391 LFR_rstn <= LFR_soft_rstn AND rstn_25;
424 LFR_rstn <= LFR_soft_rstn AND rstn_25;
392
425
393 lpp_lfr_1 : lpp_lfr
426 lpp_lfr_1 : lpp_lfr
394 GENERIC MAP (
427 GENERIC MAP (
395 Mem_use => use_RAM,
428 Mem_use => use_RAM,
396 nb_data_by_buffer_size => 32,
429 nb_data_by_buffer_size => 32,
397 --nb_word_by_buffer_size => 30,
430 --nb_word_by_buffer_size => 30,
398 nb_snapshot_param_size => 32,
431 nb_snapshot_param_size => 32,
399 delta_vector_size => 32,
432 delta_vector_size => 32,
400 delta_vector_size_f0_2 => 7, -- log2(96)
433 delta_vector_size_f0_2 => 7, -- log2(96)
401 pindex => 15,
434 pindex => 15,
402 paddr => 15,
435 paddr => 15,
403 pmask => 16#fff#,
436 pmask => 16#fff#,
404 pirq_ms => 6,
437 pirq_ms => 6,
405 pirq_wfp => 14,
438 pirq_wfp => 14,
406 hindex => 2,
439 hindex => 2,
407 top_lfr_version => X"020146") -- aa.bb.cc version
440 top_lfr_version => X"020146") -- aa.bb.cc version
408 -- AA : BOARD NUMBER
441 -- AA : BOARD NUMBER
409 -- 0 => MINI_LFR
442 -- 0 => MINI_LFR
410 -- 1 => EM
443 -- 1 => EM
411 -- 2 => EQM (with A3PE3000)
444 -- 2 => EQM (with A3PE3000)
412 PORT MAP (
445 PORT MAP (
413 clk => clk_25,
446 clk => clk_25,
414 rstn => LFR_rstn,
447 rstn => LFR_rstn,
415 sample_B => sample_s(2 DOWNTO 0),
448 sample_B => sample_s(2 DOWNTO 0),
416 sample_E => sample_s(7 DOWNTO 3),
449 sample_E => sample_s(7 DOWNTO 3),
417 sample_val => sample_val,
450 sample_val => sample_val,
418 apbi => apbi_ext,
451 apbi => apbi_ext,
419 apbo => apbo_ext(15),
452 apbo => apbo_ext(15),
420 ahbi => ahbi_m_ext,
453 ahbi => ahbi_m_ext,
421 ahbo => ahbo_m_ext(2),
454 ahbo => ahbo_m_ext(2),
422 coarse_time => coarse_time,
455 coarse_time => coarse_time,
423 fine_time => fine_time,
456 fine_time => fine_time,
424 data_shaping_BW => bias_fail_sw,
457 data_shaping_BW => bias_fail_sw,
425 debug_vector => OPEN,
458 debug_vector => OPEN,
426 debug_vector_ms => OPEN); --,
459 debug_vector_ms => OPEN); --,
427 --observation_vector_0 => OPEN,
460 --observation_vector_0 => OPEN,
428 --observation_vector_1 => OPEN,
461 --observation_vector_1 => OPEN,
429 --observation_reg => observation_reg);
462 --observation_reg => observation_reg);
430
463
431
464
432 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
465 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
433 sample_s(I) <= sample(I) & '0' & '0';
466 sample_s(I) <= sample(I) & '0' & '0';
434 END GENERATE all_sample;
467 END GENERATE all_sample;
435 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
468 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
436
469
437 -----------------------------------------------------------------------------
470 -----------------------------------------------------------------------------
438 --
471 --
439 -----------------------------------------------------------------------------
472 -----------------------------------------------------------------------------
440 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
473 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
441 GENERIC MAP (
474 GENERIC MAP (
442 ChanelCount => 9,
475 ChanelCount => 9,
443 ncycle_cnv_high => 13,
476 ncycle_cnv_high => 13,
444 ncycle_cnv => 25,
477 ncycle_cnv => 25,
445 FILTER_ENABLED => 16#FF#)
478 FILTER_ENABLED => 16#FF#)
446 PORT MAP (
479 PORT MAP (
447 cnv_clk => clk_24,
480 cnv_clk => clk_24,
448 cnv_rstn => rstn_24,
481 cnv_rstn => rstn_24,
449 cnv => ADC_smpclk_s,
482 cnv => ADC_smpclk_s,
450 clk => clk_25,
483 clk => clk_25,
451 rstn => rstn_25,
484 rstn => rstn_25,
452 ADC_data => ADC_data,
485 ADC_data => ADC_data,
453 ADC_nOE => ADC_OEB_bar_CH_s,
486 ADC_nOE => ADC_OEB_bar_CH_s,
454 sample => sample,
487 sample => sample,
455 sample_val => sample_val);
488 sample_val => sample_val);
456
489
457 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
490 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
458
491
459 ADC_smpclk <= ADC_smpclk_s;
492 ADC_smpclk <= ADC_smpclk_s;
460 HK_smpclk <= ADC_smpclk_s;
493 HK_smpclk <= ADC_smpclk_s;
461
494
462 TAG8 <= nSRAM_BUSY;
495 TAG8 <= nSRAM_BUSY;
463
496
464 -----------------------------------------------------------------------------
497 -----------------------------------------------------------------------------
465 -- HK
498 -- HK
466 -----------------------------------------------------------------------------
499 -----------------------------------------------------------------------------
467 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
500 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
468
501
469 END beh;
502 END beh;
Show file before | Show file after | Hide comments
@@ -1,213 +1,255
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25 LIBRARY ieee;
25 LIBRARY ieee;
26 USE ieee.std_logic_1164.ALL;
26 USE ieee.std_logic_1164.ALL;
27 USE ieee.numeric_std.ALL;
27 USE ieee.numeric_std.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE grlib.devices.ALL;
31 USE grlib.devices.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_amba.ALL;
34 USE lpp.lpp_amba.ALL;
35 USE lpp.apb_devices_list.ALL;
35 USE lpp.apb_devices_list.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.general_purpose.ALL;
38 USE lpp.general_purpose.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
40 LIBRARY techmap;
40 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
41 USE techmap.gencomp.ALL;
42
42
43
43
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 GENERIC (
45 GENERIC (
46 hindex : INTEGER := 2;
46 hindex : INTEGER := 2;
47 vendorid : IN INTEGER := 0;
47 vendorid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
49 version : IN INTEGER := 0
49 version : IN INTEGER := 0
50 );
50 );
51 PORT (
51 PORT (
52 clk : IN STD_LOGIC;
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54
54
55 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
58
59 -- FIFO Interface
59 -- FIFO Interface
60 ren : OUT STD_LOGIC;
60 ren : OUT STD_LOGIC;
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62
62
63 -- Controls
63 -- Controls
64 send : IN STD_LOGIC;
64 send : IN STD_LOGIC;
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 done : OUT STD_LOGIC;
66 done : OUT STD_LOGIC;
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 );
68 );
69 END;
69 END;
70
70
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72
72
73 CONSTANT HConfig : AHB_Config_Type := (
73 CONSTANT HConfig : AHB_Config_Type := (
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 OTHERS => (OTHERS => '0'));
75 OTHERS => (OTHERS => '0'));
76
76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
79
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82
82
83 SIGNAL data_window : STD_LOGIC;
83 SIGNAL data_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
85
85
86 SIGNAL bus_request : STD_LOGIC;
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
88
88
89 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
90
91 SIGNAL HREADY_pre : STD_LOGIC;
92 SIGNAL HREADY_falling : STD_LOGIC;
93
94 SIGNAL inhib_ren : STD_LOGIC;
95
89 BEGIN
96 BEGIN
90
97
91 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
92 AHB_Master_Out.HCONFIG <= HConfig;
99 AHB_Master_Out.HCONFIG <= HConfig;
93 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
100 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
94 AHB_Master_Out.HINDEX <= hindex;
101 AHB_Master_Out.HINDEX <= hindex;
95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
102 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
103 AHB_Master_Out.HIRQ <= (OTHERS => '0');
97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
104 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
98 AHB_Master_Out.HWRITE <= '1';
105 AHB_Master_Out.HWRITE <= '1';
99
106
100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
107 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101
108
102 --AHB_Master_Out.HBUSREQ <= bus_request;
109 --AHB_Master_Out.HBUSREQ <= bus_request;
103 --AHB_Master_Out.HLOCK <= data_window;
110 --AHB_Master_Out.HLOCK <= data_window;
104
111
105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
112 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
106 -- '1' WHEN ctrl_window = '1' ELSE
113 -- '1' WHEN ctrl_window = '1' ELSE
107 -- '0';
114 -- '0';
108
115
109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
116 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 -- '1' WHEN ctrl_window = '1' ELSE '0';
117 -- '1' WHEN ctrl_window = '1' ELSE '0';
111
118
112 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
120 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
121 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
115
122
116 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
124 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 --ren <= NOT beat;
125 --ren <= NOT beat;
119 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
127
128 HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
129
130
120 PROCESS (clk, rstn)
131 PROCESS (clk, rstn)
121 BEGIN -- PROCESS
132 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
133 IF rstn = '0' THEN -- asynchronous reset (active low)
123 state <= IDLE;
134 state <= IDLE;
124 done <= '0';
135 done <= '0';
136 ren <= '1';
125 address_counter_reg <= (OTHERS => '0');
137 address_counter_reg <= (OTHERS => '0');
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
138 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 AHB_Master_Out.HBUSREQ <= '0';
139 AHB_Master_Out.HBUSREQ <= '0';
128 AHB_Master_Out.HLOCK <= '0';
140 AHB_Master_Out.HLOCK <= '0';
141
142 data_reg <= (OTHERS => '0');
143
144 HREADY_pre <= '0';
145 inhib_ren <= '0';
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
146 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
147 HREADY_pre <= AHB_Master_In.HREADY;
148
149 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
150 data_reg <= data;
151 END IF;
152
130 done <= '0';
153 done <= '0';
154 ren <= '1';
155 inhib_ren <= '0';
131 CASE state IS
156 CASE state IS
132 WHEN IDLE =>
157 WHEN IDLE =>
133 AHB_Master_Out.HBUSREQ <= '0';
158 AHB_Master_Out.HBUSREQ <= '0';
134 AHB_Master_Out.HLOCK <= '0';
159 AHB_Master_Out.HLOCK <= '0';
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
160 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 address_counter_reg <= (OTHERS => '0');
161 address_counter_reg <= (OTHERS => '0');
137 IF send = '1' THEN
162 IF send = '1' THEN
163 state <= s_INIT_TRANS;
164 END IF;
165
166 WHEN s_INIT_TRANS =>
138 AHB_Master_Out.HBUSREQ <= '1';
167 AHB_Master_Out.HBUSREQ <= '1';
139 AHB_Master_Out.HLOCK <= '1';
168 AHB_Master_Out.HLOCK <= '1';
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
169 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 state <= s_ARBITER;
170 state <= s_ARBITER;
142 END IF;
143
171
144 WHEN s_ARBITER =>
172 WHEN s_ARBITER =>
145 AHB_Master_Out.HBUSREQ <= '1';
173 AHB_Master_Out.HBUSREQ <= '1';
146 AHB_Master_Out.HLOCK <= '1';
174 AHB_Master_Out.HLOCK <= '1';
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 address_counter_reg <= (OTHERS => '0');
176 address_counter_reg <= (OTHERS => '0');
149
177
150 IF AHB_Master_In.HGRANT(hindex) = '1' THEN
178 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
179 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 state <= s_CTRL;
180 state <= s_CTRL;
153 END IF;
181 END IF;
154
182
155 WHEN s_CTRL =>
183 WHEN s_CTRL =>
184 inhib_ren <= '1';
156 AHB_Master_Out.HBUSREQ <= '1';
185 AHB_Master_Out.HBUSREQ <= '1';
157 AHB_Master_Out.HLOCK <= '1';
186 AHB_Master_Out.HLOCK <= '1';
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
187 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
188 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
189 --AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 state <= s_CTRL_DATA;
190 state <= s_CTRL_DATA;
191 --ren <= '0';
162 END IF;
192 END IF;
163
193
164 WHEN s_CTRL_DATA =>
194 WHEN s_CTRL_DATA =>
165 AHB_Master_Out.HBUSREQ <= '1';
195 AHB_Master_Out.HBUSREQ <= '1';
166 AHB_Master_Out.HLOCK <= '1';
196 AHB_Master_Out.HLOCK <= '1';
167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
197 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
198 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
199 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 END IF;
200 END IF;
171
201
172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
202 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 AHB_Master_Out.HBUSREQ <= '0';
203 AHB_Master_Out.HBUSREQ <= '0';
174 AHB_Master_Out.HLOCK <= '1';--'0';
204 AHB_Master_Out.HLOCK <= '1';--'0';
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
205 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 state <= s_DATA;
206 state <= s_DATA;
177 END IF;
207 END IF;
178
208
209 ren <= HREADY_falling;
210
211 --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
212 -- ren <= '0';
213 --END IF;
214
215
179 WHEN s_DATA =>
216 WHEN s_DATA =>
217 ren <= HREADY_falling;
218
180 AHB_Master_Out.HBUSREQ <= '0';
219 AHB_Master_Out.HBUSREQ <= '0';
181 AHB_Master_Out.HLOCK <= '0';
220 --AHB_Master_Out.HLOCK <= '0';
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
221 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 IF AHB_Master_In.HREADY = '1' THEN
222 IF AHB_Master_In.HREADY = '1' THEN
223 AHB_Master_Out.HLOCK <= '0';
184 state <= IDLE;
224 state <= IDLE;
185 done <= '1';
225 done <= '1';
186 END IF;
226 END IF;
187
227
188 WHEN OTHERS => NULL;
228 WHEN OTHERS => NULL;
189 END CASE;
229 END CASE;
190 END IF;
230 END IF;
191 END PROCESS;
231 END PROCESS;
192
232
193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
233 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
234 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
195 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
196 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
236
237
238 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
197
239
198 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
199 --PROCESS (clk, rstn)
241 --PROCESS (clk, rstn)
200 --BEGIN -- PROCESS
242 --BEGIN -- PROCESS
201 -- IF rstn = '0' THEN -- asynchronous reset (active low)
243 -- IF rstn = '0' THEN -- asynchronous reset (active low)
202 -- address_counter_reg <= (OTHERS => '0');
244 -- address_counter_reg <= (OTHERS => '0');
203 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
245 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
204 -- address_counter_reg <= address_counter;
246 -- address_counter_reg <= address_counter;
205 -- END IF;
247 -- END IF;
206 --END PROCESS;
248 --END PROCESS;
207
249
208 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
250 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
209 -- address_counter_reg;
251 -- address_counter_reg;
210 -----------------------------------------------------------------------------
252 -----------------------------------------------------------------------------
211
253
212
254
213 END Behavioral;
255 END Behavioral;
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