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LFR Keypoint 3.1.89
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r632:f312a5596c4e simu_with_Leon3
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 USE techmap.axcomp.ALL;
31 31
32 32 LIBRARY gaisler;
33 33 USE gaisler.sim.ALL;
34 34 USE gaisler.memctrl.ALL;
35 35 USE gaisler.leon3.ALL;
36 36 USE gaisler.uart.ALL;
37 37 USE gaisler.misc.ALL;
38 38 USE gaisler.spacewire.ALL;
39 39 LIBRARY esa;
40 40 USE esa.memoryctrl.ALL;
41 41 LIBRARY lpp;
42 42 USE lpp.lpp_memory.ALL;
43 43 USE lpp.lpp_ad_conv.ALL;
44 44 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
45 45 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
46 46 USE lpp.iir_filter.ALL;
47 47 USE lpp.general_purpose.ALL;
48 48 USE lpp.lpp_lfr_management.ALL;
49 49 USE lpp.lpp_leon3_soc_pkg.ALL;
50 50
51 51 --library proasic3l;
52 52 --use proasic3l.all;
53 53
54 54 ENTITY LFR_EQM IS
55 55 GENERIC (
56 56 Mem_use : INTEGER := use_RAM;
57 57 USE_BOOTLOADER : INTEGER := 0;
58 58 USE_ADCDRIVER : INTEGER := 1;
59 59 tech : INTEGER := inferred;
60 60 tech_leon : INTEGER := inferred;
61 61 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
62 62 USE_DEBUG_VECTOR : INTEGER := 0
63 63 );
64 64
65 65 PORT (
66 66 clk50MHz : IN STD_ULOGIC;
67 67 clk49_152MHz : IN STD_ULOGIC;
68 68 reset : IN STD_ULOGIC;
69 69
70 70 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
71 71
72 72 -- TAG --------------------------------------------------------------------
73 73 --TAG1 : IN STD_ULOGIC; -- DSU rx data
74 74 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
75 75 -- UART APB ---------------------------------------------------------------
76 76 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
77 77 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
78 78 -- RAM --------------------------------------------------------------------
79 79 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
80 80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 81
82 82 nSRAM_MBE : INOUT STD_LOGIC; -- new
83 83 nSRAM_E1 : OUT STD_LOGIC; -- new
84 84 nSRAM_E2 : OUT STD_LOGIC; -- new
85 85 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
86 86 nSRAM_W : OUT STD_LOGIC; -- new
87 87 nSRAM_G : OUT STD_LOGIC; -- new
88 88 nSRAM_BUSY : IN STD_LOGIC; -- new
89 89 -- SPW --------------------------------------------------------------------
90 90 spw1_en : OUT STD_LOGIC; -- new
91 91 spw1_din : IN STD_LOGIC;
92 92 spw1_sin : IN STD_LOGIC;
93 93 spw1_dout : OUT STD_LOGIC;
94 94 spw1_sout : OUT STD_LOGIC;
95 95 spw2_en : OUT STD_LOGIC; -- new
96 96 spw2_din : IN STD_LOGIC;
97 97 spw2_sin : IN STD_LOGIC;
98 98 spw2_dout : OUT STD_LOGIC;
99 99 spw2_sout : OUT STD_LOGIC;
100 100 -- ADC --------------------------------------------------------------------
101 101 bias_fail_sw : OUT STD_LOGIC;
102 102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
103 103 ADC_smpclk : OUT STD_LOGIC;
104 104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
105 105 -- DAC --------------------------------------------------------------------
106 106 DAC_SDO : OUT STD_LOGIC;
107 107 DAC_SCK : OUT STD_LOGIC;
108 108 DAC_SYNC : OUT STD_LOGIC;
109 109 DAC_CAL_EN : OUT STD_LOGIC;
110 110 -- HK ---------------------------------------------------------------------
111 111 HK_smpclk : OUT STD_LOGIC;
112 112 ADC_OEB_bar_HK : OUT STD_LOGIC;
113 113 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
114 114 );
115 115
116 116 END LFR_EQM;
117 117
118 118
119 119 ARCHITECTURE beh OF LFR_EQM IS
120 120
121 121 SIGNAL clk_25_int : STD_LOGIC := '0';
122 122 SIGNAL clk_25 : STD_LOGIC := '0';
123 123 SIGNAL clk_24 : STD_LOGIC := '0';
124 124 -----------------------------------------------------------------------------
125 125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127 127
128 128 -- CONSTANTS
129 129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133 133
134 134 SIGNAL apbi_ext : apb_slv_in_type;
135 135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140 140
141 141 -- Spacewire signals
142 142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 145 SIGNAL swni : grspw_in_type;
146 146 SIGNAL swno : grspw_out_type;
147 147
148 148 --GPIO
149 149 SIGNAL gpioi : gpio_in_type;
150 150 SIGNAL gpioo : gpio_out_type;
151 151
152 152 -- AD Converter ADS7886
153 153 SIGNAL sample : Samples14v(8 DOWNTO 0);
154 154 SIGNAL sample_s : Samples(8 DOWNTO 0);
155 155 SIGNAL sample_val : STD_LOGIC;
156 156 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
157 157
158 158 -----------------------------------------------------------------------------
159 159 SIGNAL LFR_rstn_int : STD_LOGIC := '0';
160 160 SIGNAL rstn_25_int : STD_LOGIC := '0';
161 161 SIGNAL rstn_25 : STD_LOGIC;
162 162 SIGNAL rstn_24 : STD_LOGIC;
163 163
164 164 SIGNAL LFR_soft_rstn : STD_LOGIC;
165 165 SIGNAL LFR_rstn : STD_LOGIC;
166 166
167 167 SIGNAL ADC_smpclk_s : STD_LOGIC;
168 168
169 169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
170 170
171 171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
172 172
173 173 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
174 174
175 175 SIGNAL rstn_50 : STD_LOGIC;
176 176 SIGNAL clk_lock : STD_LOGIC;
177 177 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 178 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
179 179
180 180 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
181 181 SIGNAL ahbrxd: STD_LOGIC;
182 182 SIGNAL ahbtxd: STD_LOGIC;
183 183 SIGNAL urxd1 : STD_LOGIC;
184 184 SIGNAL utxd1 : STD_LOGIC;
185 185 BEGIN -- beh
186 186
187 187 -----------------------------------------------------------------------------
188 188 -- CLK_LOCK
189 189 -----------------------------------------------------------------------------
190 190 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
191 191
192 192 PROCESS (clk50MHz_int, rstn_50)
193 193 BEGIN -- PROCESS
194 194 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
195 195 clk_lock <= '0';
196 196 clk_busy_counter <= (OTHERS => '0');
197 197 nSRAM_BUSY_reg <= '0';
198 198 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
199 199 nSRAM_BUSY_reg <= nSRAM_BUSY;
200 200 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
201 201 IF clk_busy_counter = "1111" THEN
202 202 clk_lock <= '1';
203 203 ELSE
204 204 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
205 205 END IF;
206 206 END IF;
207 207 END IF;
208 208 END PROCESS;
209 209
210 210 -----------------------------------------------------------------------------
211 211 -- CLK
212 212 -----------------------------------------------------------------------------
213 213 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN);
214 214 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
215 215
216 216 rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 );
217 217
218 218 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
219 219 clk50MHz_int <= clk50MHz;
220 220
221 221 PROCESS(clk50MHz_int)
222 222 BEGIN
223 223 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
224 224 clk_25_int <= NOT clk_25_int;
225 225 --clk_25 <= NOT clk_25;
226 226 END IF;
227 227 END PROCESS;
228 228 clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 );
229 229
230 230 PROCESS(clk49_152MHz)
231 231 BEGIN
232 232 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
233 233 clk_24 <= NOT clk_24;
234 234 END IF;
235 235 END PROCESS;
236 236 -- clk_49 <= clk49_152MHz;
237 237
238 238 -----------------------------------------------------------------------------
239 239 leon3_soc_1 : leon3_soc
240 240 GENERIC MAP (
241 241 fabtech => axcel,--inferred,--axdsp,
242 242 memtech => axcel,--inferred,--tech_leon,
243 243 padtech => axcel,--inferred,
244 244 clktech => axcel,--inferred,
245 245 disas => 0,
246 246 dbguart => 0,
247 247 pclow => 2,
248 248 clk_freq => 25000,
249 249 IS_RADHARD => 1,
250 250 NB_CPU => 1,
251 251 ENABLE_FPU => 1,
252 252 FPU_NETLIST => 0,
253 253 ENABLE_DSU => 1,
254 254 ENABLE_AHB_UART => 0,
255 255 ENABLE_APB_UART => 1,
256 256 ENABLE_IRQMP => 1,
257 257 ENABLE_GPT => 1,
258 258 NB_AHB_MASTER => NB_AHB_MASTER,
259 259 NB_AHB_SLAVE => NB_AHB_SLAVE,
260 260 NB_APB_SLAVE => NB_APB_SLAVE,
261 261 ADDRESS_SIZE => 19,
262 262 USES_IAP_MEMCTRLR => 1,
263 263 BYPASS_EDAC_MEMCTRLR => '0',
264 264 SRBANKSZ => 8)
265 265 PORT MAP (
266 266 clk => clk_25,
267 267 reset => rstn_25,
268 268 errorn => OPEN,
269 269
270 270 ahbrxd => ahbrxd, -- INPUT
271 271 ahbtxd => ahbtxd, -- OUTPUT
272 272 urxd1 => urxd1, -- INPUT
273 273 utxd1 => utxd1, -- OUTPUT
274 274
275 275 address => address,
276 276 data => data,
277 277 nSRAM_BE0 => OPEN,
278 278 nSRAM_BE1 => OPEN,
279 279 nSRAM_BE2 => OPEN,
280 280 nSRAM_BE3 => OPEN,
281 281 nSRAM_WE => nSRAM_W,
282 282 nSRAM_CE => nSRAM_CE,
283 283 nSRAM_OE => nSRAM_G,
284 284 nSRAM_READY => nSRAM_BUSY,
285 285 SRAM_MBE => nSRAM_MBE,
286 286
287 287 apbi_ext => apbi_ext,
288 288 apbo_ext => apbo_ext,
289 289 ahbi_s_ext => ahbi_s_ext,
290 290 ahbo_s_ext => ahbo_s_ext,
291 291 ahbi_m_ext => ahbi_m_ext,
292 292 ahbo_m_ext => ahbo_m_ext);
293 293
294 294
295 295 nSRAM_E1 <= nSRAM_CE(0);
296 296 nSRAM_E2 <= nSRAM_CE(1);
297 297
298 298 -------------------------------------------------------------------------------
299 299 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
300 300 -------------------------------------------------------------------------------
301 301 apb_lfr_management_1 : apb_lfr_management
302 302 GENERIC MAP (
303 303 tech => tech,
304 304 pindex => 6,
305 305 paddr => 6,
306 306 pmask => 16#fff#,
307 307 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
308 308 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
309 309 PORT MAP (
310 310 clk25MHz => clk_25,
311 311 resetn_25MHz => rstn_25, -- TODO
312 312 --clk24_576MHz => clk_24, -- 49.152MHz/2
313 313 --resetn_24_576MHz => rstn_24, -- TODO
314 314
315 315 grspw_tick => swno.tickout,
316 316 apbi => apbi_ext,
317 317 apbo => apbo_ext(6),
318 318
319 319 HK_sample => sample_s(8),
320 320 HK_val => sample_val,
321 321 HK_sel => HK_SEL,
322 322
323 323 DAC_SDO => DAC_SDO,
324 324 DAC_SCK => DAC_SCK,
325 325 DAC_SYNC => DAC_SYNC,
326 326 DAC_CAL_EN => DAC_CAL_EN,
327 327
328 328 coarse_time => coarse_time,
329 329 fine_time => fine_time,
330 330 LFR_soft_rstn => LFR_soft_rstn
331 331 );
332 332
333 333 -----------------------------------------------------------------------
334 334 --- SpaceWire --------------------------------------------------------
335 335 -----------------------------------------------------------------------
336 336
337 337 ------------------------------------------------------------------------------
338 338 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
339 339 ------------------------------------------------------------------------------
340 340 spw1_en <= '1';
341 341 spw2_en <= '1';
342 342 ------------------------------------------------------------------------------
343 343 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
344 344 ------------------------------------------------------------------------------
345 345
346 346 --spw_clk <= clk50MHz;
347 347 --spw_rxtxclk <= spw_clk;
348 348 --spw_rxclkn <= NOT spw_rxtxclk;
349 349
350 350 -- PADS for SPW1
351 351 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
352 352 PORT MAP (spw1_din, dtmp(0));
353 353 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
354 354 PORT MAP (spw1_sin, stmp(0));
355 355 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
356 356 PORT MAP (spw1_dout, swno.d(0));
357 357 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
358 358 PORT MAP (spw1_sout, swno.s(0));
359 359 -- PADS FOR SPW2
360 360 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
361 361 PORT MAP (spw2_din, dtmp(1));
362 362 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
363 363 PORT MAP (spw2_sin, stmp(1));
364 364 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
365 365 PORT MAP (spw2_dout, swno.d(1));
366 366 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
367 367 PORT MAP (spw2_sout, swno.s(1));
368 368
369 369 -- GRSPW PHY
370 370 --spw1_input: if CFG_SPW_GRSPW = 1 generate
371 371 spw_inputloop : FOR j IN 0 TO 1 GENERATE
372 372 spw_phy0 : grspw_phy
373 373 GENERIC MAP(
374 374 tech => axcel,-- inferred,--axdsp,--tech_leon,
375 375 rxclkbuftype => 1,
376 376 scantest => 0)
377 377 PORT MAP(
378 378 rxrst => swno.rxrst,
379 379 di => dtmp(j),
380 380 si => stmp(j),
381 381 rxclko => spw_rxclk(j),
382 382 do => swni.d(j),
383 383 ndo => swni.nd(j*5+4 DOWNTO j*5),
384 384 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
385 385 END GENERATE spw_inputloop;
386 386
387 387 -- SPW core
388 388 sw0 : grspwm GENERIC MAP(
389 389 tech => axcel,--inferred,--axdsp,--tech_leon,
390 390 hindex => 1,
391 391 pindex => 5,
392 392 paddr => 5,
393 393 pirq => 11,
394 394 sysfreq => 25000, -- CPU_FREQ
395 395 rmap => 1,
396 396 rmapcrc => 1,
397 397 fifosize1 => 16,
398 398 fifosize2 => 16,
399 399 rxclkbuftype => 1,
400 400 rxunaligned => 0,
401 401 rmapbufs => 4,
402 402 ft => 1,
403 403 netlist => 0,
404 404 ports => 2,
405 405 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
406 406 memtech => axcel,--inferred,--tech_leon,
407 407 destkey => 2,
408 408 spwcore => 1
409 409 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
410 410 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
411 411 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
412 412 )
413 413 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
414 414 spw_rxclk(1),
415 415 clk50MHz_int,
416 416 clk50MHz_int,
417 417 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
418 418 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
419 419 swni, swno);
420 420
421 421 swni.tickin <= '0';
422 422 swni.rmapen <= '1';
423 423 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
424 424 swni.tickinraw <= '0';
425 425 swni.timein <= (OTHERS => '0');
426 426 swni.dcrstval <= (OTHERS => '0');
427 427 swni.timerrstval <= (OTHERS => '0');
428 428
429 429 -------------------------------------------------------------------------------
430 430 -- LFR ------------------------------------------------------------------------
431 431 -------------------------------------------------------------------------------
432 432 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
433 433 LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int;
434 434
435 435 rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn );
436 436
437 437 lpp_lfr_1 : lpp_lfr
438 438 GENERIC MAP (
439 439 Mem_use => Mem_use,
440 440 tech => inferred,--tech,
441 441 nb_data_by_buffer_size => 32,
442 442 --nb_word_by_buffer_size => 30,
443 443 nb_snapshot_param_size => 32,
444 444 delta_vector_size => 32,
445 445 delta_vector_size_f0_2 => 7, -- log2(96)
446 446 pindex => 15,
447 447 paddr => 15,
448 448 pmask => 16#fff#,
449 449 pirq_ms => 6,
450 450 pirq_wfp => 14,
451 451 hindex => 2,
452 top_lfr_version => X"020159", -- aa.bb.cc version
452 top_lfr_version => X"030159", -- aa.bb.cc version
453 453 -- AA : BOARD NUMBER
454 454 -- 0 => MINI_LFR
455 455 -- 1 => EM
456 456 -- 2 => EQM (with A3PE3000)
457 457 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
458 458 RTL_DESIGN_LIGHT =>0,
459 459 WINDOWS_HAANNING_PARAM_SIZE => 15)
460 460 PORT MAP (
461 461 clk => clk_25,
462 462 rstn => LFR_rstn,
463 463 sample_B => sample_s(2 DOWNTO 0),
464 464 sample_E => sample_s(7 DOWNTO 3),
465 465 sample_val => sample_val,
466 466 apbi => apbi_ext,
467 467 apbo => apbo_ext(15),
468 468 ahbi => ahbi_m_ext,
469 469 ahbo => ahbo_m_ext(2),
470 470 coarse_time => coarse_time,
471 471 fine_time => fine_time,
472 472 data_shaping_BW => bias_fail_sw,
473 473 debug_vector => debug_vector,
474 474 debug_vector_ms => OPEN); --,
475 475 --observation_vector_0 => OPEN,
476 476 --observation_vector_1 => OPEN,
477 477 --observation_reg => observation_reg);
478 478
479 479
480 480 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
481 481 sample_s(I) <= sample(I) & '0' & '0';
482 482 END GENERATE all_sample;
483 483 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
484 484
485 485 -----------------------------------------------------------------------------
486 486 --
487 487 -----------------------------------------------------------------------------
488 488 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
489 489 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
490 490 GENERIC MAP (
491 491 ChanelCount => 9,
492 492 ncycle_cnv_high => 12,
493 493 ncycle_cnv => 25,
494 494 FILTER_ENABLED => 16#FF#)
495 495 PORT MAP (
496 496 cnv_clk => clk_24,
497 497 cnv_rstn => rstn_24,
498 498 cnv => ADC_smpclk_s,
499 499 clk => clk_25,
500 500 rstn => rstn_25,
501 501 ADC_data => ADC_data,
502 502 ADC_nOE => ADC_OEB_bar_CH_s,
503 503 sample => sample,
504 504 sample_val => sample_val);
505 505
506 506 END GENERATE USE_ADCDRIVER_true;
507 507
508 508 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
509 509 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
510 510 GENERIC MAP (
511 511 ChanelCount => 9,
512 512 ncycle_cnv_high => 25,
513 513 ncycle_cnv => 50,
514 514 FILTER_ENABLED => 16#FF#)
515 515 PORT MAP (
516 516 cnv_clk => clk_24,
517 517 cnv_rstn => rstn_24,
518 518 cnv => ADC_smpclk_s,
519 519 clk => clk_25,
520 520 rstn => rstn_25,
521 521 ADC_data => ADC_data,
522 522 ADC_nOE => OPEN,
523 523 sample => OPEN,
524 524 sample_val => sample_val);
525 525
526 526 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
527 527
528 528 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
529 529 ramp_generator_1: ramp_generator
530 530 GENERIC MAP (
531 531 DATA_SIZE => 14,
532 532 VALUE_UNSIGNED_INIT => 2**I,
533 533 VALUE_UNSIGNED_INCR => 0,
534 534 VALUE_UNSIGNED_MASK => 16#3FFF#)
535 535 PORT MAP (
536 536 clk => clk_25,
537 537 rstn => rstn_25,
538 538 new_data => sample_val,
539 539 output_data => sample(I) );
540 540 END GENERATE all_sample;
541 541
542 542
543 543 END GENERATE USE_ADCDRIVER_false;
544 544
545 545
546 546
547 547
548 548 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
549 549
550 550 ADC_smpclk <= ADC_smpclk_s;
551 551 HK_smpclk <= ADC_smpclk_s;
552 552
553 553
554 554 -----------------------------------------------------------------------------
555 555 -- HK
556 556 -----------------------------------------------------------------------------
557 557 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
558 558
559 559 -----------------------------------------------------------------------------
560 560 --
561 561 -----------------------------------------------------------------------------
562 562 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
563 563 -- lpp_bootloader_1: lpp_bootloader
564 564 -- GENERIC MAP (
565 565 -- pindex => 13,
566 566 -- paddr => 13,
567 567 -- pmask => 16#fff#,
568 568 -- hindex => 3,
569 569 -- haddr => 0,
570 570 -- hmask => 16#fff#)
571 571 -- PORT MAP (
572 572 -- HCLK => clk_25,
573 573 -- HRESETn => rstn_25,
574 574 -- apbi => apbi_ext,
575 575 -- apbo => apbo_ext(13),
576 576 -- ahbsi => ahbi_s_ext,
577 577 -- ahbso => ahbo_s_ext(3));
578 578 --END GENERATE inst_bootloader;
579 579
580 580 -----------------------------------------------------------------------------
581 581 --
582 582 -----------------------------------------------------------------------------
583 583 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
584 584 PROCESS (clk_25, rstn_25)
585 585 BEGIN -- PROCESS
586 586 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
587 587 TAG <= (OTHERS => '0');
588 588 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
589 589 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
590 590 END IF;
591 591 END PROCESS;
592 592
593 593
594 594 END GENERATE USE_DEBUG_VECTOR_IF;
595 595
596 596 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
597 597 --ahbrxd <= TAG(1); -- AHB UART
598 598 --TAG(3) <= ahbtxd;
599 599
600 600 urxd1 <= TAG(2); -- APB UART
601 601 TAG(4) <= utxd1;
602 602 --TAG(8) <= nSRAM_BUSY;
603 603 END GENERATE USE_DEBUG_VECTOR_IF2;
604 604
605 605 END beh; No newline at end of file
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