| @@ -83,11 +83,11 ENTITY lpp_top_apbreg IS | |||
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83 | 83 | --------------------------------------------------------------------------- |
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84 | 84 | --------------------------------------------------------------------------- |
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85 | 85 | -- WaveForm picker Reg |
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86 |
status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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86 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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87 | 87 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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88 | 88 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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89 | 89 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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90 | ||
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90 | ||
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91 | 91 | -- OUT |
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92 | 92 | data_shaping_BW : OUT STD_LOGIC; |
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93 | 93 | data_shaping_SP0 : OUT STD_LOGIC; |
| @@ -191,33 +191,33 BEGIN -- beh | |||
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191 | 191 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; |
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192 | 192 | |
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193 | 193 | |
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194 | ||
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195 | ||
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196 | data_shaping_BW <= reg_wp.data_shaping_BW; | |
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197 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
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198 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
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199 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
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200 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
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194 | ||
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201 | 195 | |
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202 |
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203 | delta_f2_f1 <= reg_wp.delta_f2_f1; | |
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204 | delta_f2_f0 <= reg_wp.delta_f2_f0; | |
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205 | nb_burst_available <= reg_wp.nb_burst_available; | |
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206 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
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196 | data_shaping_BW <= reg_wp.data_shaping_BW; | |
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197 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |
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198 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |
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199 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |
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200 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |
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201 | ||
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202 | delta_snapshot <= reg_wp.delta_snapshot; | |
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203 | delta_f2_f1 <= reg_wp.delta_f2_f1; | |
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204 | delta_f2_f0 <= reg_wp.delta_f2_f0; | |
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205 | nb_burst_available <= reg_wp.nb_burst_available; | |
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206 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |
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207 | 207 | |
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208 |
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209 |
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210 |
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211 |
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208 | enable_f0 <= reg_wp.enable_f0; | |
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209 | enable_f1 <= reg_wp.enable_f1; | |
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210 | enable_f2 <= reg_wp.enable_f2; | |
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211 | enable_f3 <= reg_wp.enable_f3; | |
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212 | 212 | |
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213 |
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214 |
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215 |
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213 | burst_f0 <= reg_wp.burst_f0; | |
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214 | burst_f1 <= reg_wp.burst_f1; | |
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215 | burst_f2 <= reg_wp.burst_f2; | |
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216 | 216 | |
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217 |
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218 |
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219 |
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220 |
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217 | addr_data_f0 <= reg_wp.addr_data_f0; | |
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218 | addr_data_f1 <= reg_wp.addr_data_f1; | |
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219 | addr_data_f2 <= reg_wp.addr_data_f2; | |
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220 | addr_data_f3 <= reg_wp.addr_data_f3; | |
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221 | 221 | |
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222 | 222 | lpp_top_apbreg : PROCESS (HCLK, HRESETn) |
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223 | 223 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
| @@ -238,28 +238,28 BEGIN -- beh | |||
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238 | 238 | prdata <= (OTHERS => '0'); |
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239 | 239 | |
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240 | 240 | apbo.pirq <= (OTHERS => '0'); |
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241 | ||
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241 | ||
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242 | 242 | status_full_ack <= (OTHERS => '0'); |
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243 | ||
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244 | reg_wp.data_shaping_BW <= '0'; | |
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245 | reg_wp.data_shaping_SP0 <= '0'; | |
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246 | reg_wp.data_shaping_SP1 <= '0'; | |
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247 | reg_wp.data_shaping_R0 <= '0'; | |
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248 | reg_wp.data_shaping_R1 <= '0'; | |
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249 | reg_wp.enable_f0 <= '0'; | |
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250 | reg_wp.enable_f1 <= '0'; | |
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251 | reg_wp.enable_f2 <= '0'; | |
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252 | reg_wp.enable_f3 <= '0'; | |
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253 | reg_wp.burst_f0 <= '0'; | |
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254 | reg_wp.burst_f1 <= '0'; | |
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255 | reg_wp.burst_f2 <= '0'; | |
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256 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
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257 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
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258 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
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259 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
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260 | reg_wp.status_full <= (OTHERS => '0'); | |
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261 | reg_wp.status_full_err <= (OTHERS => '0'); | |
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262 | reg_wp.status_new_err <= (OTHERS => '0'); | |
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243 | ||
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244 | reg_wp.data_shaping_BW <= '0'; | |
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245 | reg_wp.data_shaping_SP0 <= '0'; | |
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246 | reg_wp.data_shaping_SP1 <= '0'; | |
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247 | reg_wp.data_shaping_R0 <= '0'; | |
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248 | reg_wp.data_shaping_R1 <= '0'; | |
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249 | reg_wp.enable_f0 <= '0'; | |
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250 | reg_wp.enable_f1 <= '0'; | |
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251 | reg_wp.enable_f2 <= '0'; | |
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252 | reg_wp.enable_f3 <= '0'; | |
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253 | reg_wp.burst_f0 <= '0'; | |
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254 | reg_wp.burst_f1 <= '0'; | |
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255 | reg_wp.burst_f2 <= '0'; | |
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256 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |
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257 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |
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258 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |
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259 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |
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260 | reg_wp.status_full <= (OTHERS => '0'); | |
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261 | reg_wp.status_full_err <= (OTHERS => '0'); | |
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262 | reg_wp.status_new_err <= (OTHERS => '0'); | |
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263 | 263 | reg_wp.delta_snapshot <= (OTHERS => '0'); |
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264 | 264 | reg_wp.delta_f2_f1 <= (OTHERS => '0'); |
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265 | 265 | reg_wp.delta_f2_f0 <= (OTHERS => '0'); |
| @@ -271,8 +271,8 BEGIN -- beh | |||
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271 | 271 | |
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272 | 272 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
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273 | 273 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
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274 |
reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 |
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275 |
reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 |
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274 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |
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275 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |
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276 | 276 | |
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277 | 277 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
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278 | 278 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
| @@ -341,12 +341,12 BEGIN -- beh | |||
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341 | 341 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); |
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342 | 342 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); |
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343 | 343 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); |
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344 |
WHEN "000010" => reg_sp.addr_matrix_f0_0 |
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345 |
WHEN "000011" => reg_sp.addr_matrix_f0_1 |
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346 |
WHEN "000100" => reg_sp.addr_matrix_f1 |
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347 |
WHEN "000101" => reg_sp.addr_matrix_f2 |
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344 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
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345 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
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346 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |
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347 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |
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348 | 348 | -- |
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349 | WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
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349 | WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
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350 | 350 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
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351 | 351 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
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352 | 352 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
| @@ -365,10 +365,10 BEGIN -- beh | |||
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365 | 365 | WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); |
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366 | 366 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
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367 | 367 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
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368 |
status_full_ack(0) <= reg_wp.status_full(0) AND |
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369 |
status_full_ack(1) <= reg_wp.status_full(1) AND |
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370 |
status_full_ack(2) <= reg_wp.status_full(2) AND |
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371 |
status_full_ack(3) <= reg_wp.status_full(3) AND |
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368 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |
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369 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |
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370 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |
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371 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |
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372 | 372 | WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0); |
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373 | 373 | WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0); |
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374 | 374 | WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0); |
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